Editor: Bob Wheeler In This Issue A Guide to FPGAs for Communications is now available for immediate delivery. Get our analysis, comparisons, and conclusions on midrange and high-end FPGAs used in wireless and wireline infrastructure systems. For more information, visit our web site. At Interop, Broadcom announced availability of its XGS Core fabric, which extends the StrataXGS architecture from high-volume enterprise switches to the network core. The XGS Core consists of a fabric interface chip (BCM88200), a central switch (BCM88100), and a buffer manager (BCM56900). These components combine with Broadcom's BCM88025 forwarding engine and PHYs to provide the most complete switching solution for the data center and the enterprise. The BCM88200 is an 80Gbps full-duplex fabric-interface chip and traffic manager. This capacity enables multiple-port 10GbE and 40GbE line cards. The chip provides a DDR3 interface for an external buffer that supports up to 200ms hold time. The large hold time helps improve performance in congested environments. For fine-grained traffic management, the BCM88200 supports up to 64,000 queues, which can be segmented for Hierarchical-QoS support. The fabric interface chip connects to the central switch using 24 lanes of 6.56Gbps serdes. The BCM88100 is a bufferless crossbar switch with an integrated central scheduler. The central scheduler can provide guarantees for data rate and latency through the fabric. The scheduling algorithm can converge to support data flows at 40GbE as well as at 100GbE—enabling OEMs to scale their systems for future services. The device supports both TDM and packet traffic, enabling a converged fabric for multiple services. The switch provides 96 lanes of 6.56Gbps serdes to connect with multiple BCM88200 chips. Broadcom's fabric requires an overspeed of only 1.25x, instead of the traditional 2x overspeed required by legacy fabrics. The lower overspeed results in better utilization of the raw bandwidth within the fabric. Using multiple fabric-interface and switch devices, OEMs can build systems that scale beyond 10Tbps. The buffer device, BCM56900, is designed for use with the StrataXGS Ethernet-switch family. It adds an external buffer and traffic manager to the StrataXGS devices—extending existing StrataXGS designs with improved traffic handling to support SLAs. The XGS Core and StrataXGS devices all use a common API—enabling customers to reuse software across platforms for a faster time to market. Since acquiring Sandburst in 2006, Broadcom has released few public details of its fabric and core products. By far, this is Broadcom's biggest announcement for fabrics and a significant development in the fabric market. It reveals a leading fabric solution for data center, enterprise backbone, and Carrier Ethernet switching. The XGS Core fabric supports bandwidth requirements for most applications today and is architected to support emerging ports rates such as 100GbE. For OEMs that already use StrataXGS switches, an additional bonus is the ability to easily port software across different platforms. —Jag Additional coverage of Broadcom's Ethernet products appears in our report A Guide to Ethernet Switch and PHY Chips. EEMBC recently announced its first open benchmark, called CoreMark. According to EEMBC, the benchmark is "small, yet sophisticated" and can be easily ported to run on a variety of CPUs, from 8-bit microcontrollers to 32-bit embedded processors. Since its formation in 1997, EEMBC has sought to provide rigorous benchmarks that could be used in place of Dhrystone to better measure the performance of embedded processors. As most of you know, Dhrystone has many failings, including a susceptibility to compiler optimizations and a lack of memory operations. Although EEMBC has produced a slew of well-respected benchmarks covering automotive, consumer, multimedia, networking, and other applications, Dhrystone continues to be widely quoted, even by EEMBC member companies. The problem lies in EEMBC's publication process. EEMBC members may not publish a score unless it has been certified by EEMBC. Because certification costs money, processor vendors are not motivated to certify their scores unless they achieve industry leadership. Thus, the number of published scores has slowed to a trickle in recent years. Many vendors publish scores for some benchmarks but not others, further limiting the opportunity to make comparisons. To avoid the certification process, most EEMBC members share their scores with potential customers only under NDA. To generate comparison data, each vendor then has to run the benchmarks on their competitors' products. This situation creates many opportunities for cheating, since none of the results is certified or vetted in any way. Thus, large customers must rerun the benchmarks themselves to verify the results. Dhrystone remains the only benchmark that is consistently and publicly available for all CPUs. The new CoreMark aims to solve this problem by eliminating the certification requirement and offering the benchmark source code openly. CoreMark results can be generated and published by any vendor, customer, or developer, which should quickly create a large body of scores. Once that happens, perhaps we can finally bury Dhrystone for good. CoreMark is not as thorough as the traditional EEMBC benchmarks, however; for example, it does not show the impact of memory, I/O, and application-specific functions. Markus Levy, the president of EEMBC, hopes that CoreMark will prove to be a free sample that entices more vendors to use and publish results for other EEMBC benchmarks. As someone who compares microprocessors for a living, I hope he's right. —Linley For additional information on CoreMark, visit http://www.coremark.org This month, Gennum announced availability of the industry's first PCIe 3.0 IP cores. PCIe 3.0 doubles the bandwidth from the previous generation (Gen2) and includes several enhancements. These include power management enhancements, latency and real-throughput improvements, and enhancements for handling multicast packets. Gennum's solution consists of hardened IP for the Physical layer and synthesizable IP for the controller or link and protocol layers. The PCIe 3.0 IP was developed for TSMC's 40nm process technology and can be ported to other technologies. PLX Technology, the first announced licensee, likely drove the choice of the foundry and process technology. Gennum offers its PCIe 3.0 IP as an endpoint, root, and switch for x1, x4, x8, or x16 lane configurations. The PHY design includes transmit pre-emphasis and adaptive equalizers to ensure good signal integrity. With its PCIe 3.0 IP and previously announced 10Gbps IP, Gennum has established a solid foundation for mixed-signal products. —Jag To receive Linley Wire via e-mail, click here
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