Editor: Linley Gwennap In This Issue
What do trends like cloud computing, virtualization, and network convergence mean to your next design? Beyond buzzwords, these trends have very real implications for all types of data-center networking systems and servers. For help sorting all this out, mark your calendar for the inaugural Linley Tech Spring Conference coming to San Jose on May 18-19. Hear presentations from AppliedMicro, LSI, Netronome, NetLogic Microsystems, Freescale, Cavium Networks, Intel, Xilinx, Marvell, Chelsio, Teranetics, Fulcrum Microsystems, and more. Program to be announced shortly. Tabula Time-Slices FPGA to Add Density Emerging from stealth mode, Tabula last week disclosed its first FPGA products based on its innovative Spacetime architecture. The new ABAX products, expected to sample in 3Q10, can match the gate count of Xilinx's largest FPGAs at a fraction of the price. Tabula's devices can operate at 1.6GHz, compared to 400-500MHz for traditional FPGAs. Instead of focusing on speed, the Spacetime architecture time-slices the RTL design. A 200MHz design, for example, can have eight time slices. The same gate (LUT in FPGA terminology) can perform a different function in each time slice, acting as eight virtual LUTs. Although this approach requires eight times as much configuration SRAM per physical LUT, the net result is much lower cost and lower power dissipation. The company claims the overall density of its products will be 2.5 times greater than that of conventional FPGAs from Xilinx and Altera. Developed in leading-edge 40nm technology, ABAX includes four products that offer different densities for LUTs and multipliers. The A1EC06 offers the greatest density with 630K LUTs and 1,280 (18x18) multipliers at a price of $200, several times cheaper than comparable devices from Altera and Xilinx. All four ABAX devices support 48 serdes lanes at 6.5Gbps and up to 920 parallel I/Os. Tabula has worked with third parties to line up soft IP for several popular functions, including memory control, PCI Express Gen 1 and Gen 2, GbE and 10GbE Ethernet MACs, RapidIO, and Freescale's ColdFire CPU. Initial target applications for ABAX include cellular baseband processing and packet processing. Tabula's FPGAs use similar design tools as other FPGAs and ASICs, so the logic designer does not need to learn new processes. Tabula's challenge is to automatically create a space/time version of a space-only RTL design. The synthesized design must communicate between the segmented designs in each time slot in the same manner as the original design. These requirements place a heavy burden on Tabula's back-end (route and place) tools. Tabula seeks to significantly reduce FPGA cost by innovating at the architecture level. The toughest technical challenge for the company is to validate its tools for synthesis and debugging. At the business level, Tabula must to convince third parties to port their IP to the startup's platform. For OEMs that have the complete IP package in house, Tabula offers a way to slash the cost of large FPGA-based designs. —Jag Additional coverage of the FPGA market appears in our report A Guide to FPGAs for Communications.
Perhaps spurred by Tabula's announcement, Tier Logic recently came out of stealth mode to discuss its technology for reducing the cost of FPGAs. Although both companies use the term 3D to describe their approaches, Tabula uses time as its third dimension, whereas Tier works in the more traditional third dimension of verticality. Tier has developed a new process step in the fabrication of silicon, creating a layer of SRAM cells on top of the metal layers. The company claims that the cost of this additional processing is more than offset by its benefits. Removing the configuration SRAM from the base level of the FPGA reduces die size, the number of interconnects, power dissipation, and cost. In addition, the configuration SRAM can be made larger, resulting in more bits per LUT. These extra bits add configuration options, improving LUT utilization. Combining the die-space reduction and better utilization, the company estimates that the overall benefit is 1.8x (vs. low-end architectures) to 3.5x (vs. high-end) compared with conventional FPGAs. The new architecture also provides a simple migration path from FPGA to ASIC. When a customer wants to further reduce cost by migrating to an ASIC, Tier simply changes the configuration SRAM layer to a metal layer; the rest of the design remains the same. Thus, the process to move into an ASIC is about a month, compared to nine months for Altera's HardCopy. To engage customers, the startup has a limited time offer to convert FPGA designs to ASICs for no charge. With limited funding, the startup is using an older 90nm process for its initial products, which target mid-range FPGA applications. Tier is currently debugging its first silicon and expects to sample FPGA products in 2Q10. The company offers an appealing value proposition: lower cost than conventional FPGAs and a no-risk migration to an even lower cost ASICs. Tier faces many of the same challenges as Tabula but has fewer resources with which to develop its innovative technology. —Jag For our take on how this announcement impacts Xilinx and Altera, see our blog post Innovation Threatens FPGA Duopoly.
This week, Chelsio announced its fourth-generation Terminator chip, or T4, which is due to sample in Q2. Targeting LAN-on-motherboard designs, the 65nm chip supports memory-free configurations while still handling all stateful offloads. Chelsio's shipping T3 chip supports TCP offload (TOE), iSCSI acceleration, and iWARP/RDMA; T4 adds support for Fibre Channel over Ethernet with full offload. Through internal design enhancements, Chelsio has reduced RDMA latency to an estimated two microseconds. The new chip also adds features for virtualization, including SR-IOV support and an embedded Layer 2 switch (or vSwitch). To support line-rate operation for dual 10GbE ports, T4 includes a Gen2 PCIe x8 interface that provides up to 32Gbps of bandwidth. In an industry first, T4 actually includes four 10GbE ports that can be combined using link aggregation. All four network ports include 10Gbps serdes for direct connection to SFP+ modules and 10GBase-KR backplanes. The multispeed network ports can also be used in GbE+10GbE combinations such as a 2xGbE LOM design with 10GbE upgrade options. By integrating a TCAM and buffer memory, T4 supports its full performance while offloading up to 1K connections in a single-chip design. For NICs or storage targets that require more offloaded connections, T4 supports external DDR2/3 SDRAM memory expansion. Chelsio's T4 stands out as the industry's first 10GbE controller to fully offload all types of storage and cluster traffic. Most competing chips are optimized for only one protocol, which limits flexibility for both OEMs and end users. But delivering T4 and all of its accompanying software is an ambitious undertaking for a small company. In particular, Chelsio is developing its Fibre Channel driver for FCoE from scratch and must qualify this stack with storage vendors. By comparison, the converged network adapters from QLogic and Emulex use field-proven FC drivers. On the other hand, these competitors lack iWARP support and Chelsio's proven software for that protocol. Assuming it delivers this universal design as specified, Chelsio will be able to tap multiple markets to accelerate its growth. —Bob Chelsio will give a talk on network convergence and T4 at our Linley Tech Spring Conference in San Jose on May 18-19. Last week, Netronome announced it is sampling the new NFP32xx line, which is based on Intel's market-leading IXP network-processor architecture. The top-of-the-line NFP3240 more than doubles the performance of Intel's IXP28xx, whereas the NFP3216 can serve as a direct replacement for the Intel NPU. The NFP32xx reduces system cost by using commodity DDR3 SDRAM in place of the Rambus DRAM and QDR SRAM required by its Intel predecessor. Netronome has made many other architectural enhancements including adding a high-performance PCIe interface that supports I/O virtualization. Netronome claims NFP design wins at top-tier OEMs and expects the first of these to reach production in 2H10. —Bob Coverage of Netronome appears in our new report A Guide to Network Processors.
Network processors have become a critical ingredient of carrier-equipment designs. These chips are appearing in new designs from leading OEMs spanning many applications from PON OLTs and Node Bs to Carrier Ethernet switch/routers. This broad adoption has created a merchant NPU market that exceeded $300 million in 2009, large enough to sustain multiple vendors. Yet many large vendors have abandoned the market, leaving excellent opportunities for more focused vendors. Access infrastructure is migrating to Ethernet and IP backhaul while data rates for both wireline and wireless networks continue to climb. These factors are driving the need for new access NPUs that are more similar to metro-class NPUs. Meanwhile, metro-class NPUs are scaling to 100Gbps and beyond to support high-density line cards and emerging 40G/100G Ethernet. A Guide to Network Processors provides a single comprehensive report covering NPUs spanning data rates from 2Gbps to 100Gbps. This report covers the vendors and products that address multiple markets using programmable designs including: Broadcom's XGS Core line, LSI's APP and Axxia lines, Wintegra's WinPath, EZchip's NPA and NP lines, Netronome's NFP (Intel IXP derivative), and Xelerated's HX and AX lines. We also cover vendors of FPGA-based chips that compete with NPUs in some designs, including Ethernity and Tpack. Included in this edition is new quantitative market data, including NPU market share updated for 2009, market segmentation by application and performance, plus a forecast for merchant NPUs through 2014. "A Guide to Network Processors" gives you the inside story on this market. Which major vendors are in this business for the long haul? Which startups will survive? How do the latest products stack up? If you are interested in following this strategic standard-product segment, you have located the definitive source. Order by April 23 to take advantage of the introductory offer. For more information on this new edition, visit our web site. Latest Posts from our Blog, Linley Chips In:
To receive Linley Wire via e-mail, click here
|
