The Linley Group

A Guide to Backplane Switch Chips, Fifth Edition

List of Figures

Return to
Report Page

Figure 1-1 Generic network architecture
1

Figure 1-2 3GPP Release 5 IP multimedia network architecture
6

Figure 1-3 Typical LAN architecture
7

Figure 2-1 System architecture and interfaces
12

Figure 2-2 Current blade-server architecture
13

Figure 2-3 Converged blade-server design
14

Figure 2-4 RSVP host and router implementation
18

Figure 2-5 Logical diagrams of dual-star (left) and mesh topologies
19

Figure 2-6 Interconnect examples using RapidIO
25

Figure 2-7 RapidIO three-layer model
26

Figure 3-1 Switch-fabric architecture and chip partitioning
37

Figure 3-2 Three-stage Clos architecture
43

Figure 3-3 Fabric latency versus load for generic fabric
44

Figure 4-1 Fabric-market revenue share by vendor for 2004 and 2005
54

Figure 5-1 AMCC PRS product-line evolution
59

Figure 5-2 AMCC PRS-80G internal architecture
61

Figure 5-3 AMCC C192X internal architecture
62

Figure 5-4 AMCC PRS-Q80G system design
63

Figure 5-5 AMCC PRS-5G latency versus load
65

Figure 6-1 Broadcom HiBeam packet fabric
71

Figure 6-2 Broadcom HiBeam system design
73

Figure 8-1 Fujitsu’s MB8AAQ3020 block diagram
84

Figure 8-2 Fujitsu’s 3020 in an ATCA system
86

Figure 9-1 Fulcum FocalPoint internal architecture
91

Figure 9-2 Fulcrum FM2224 in a mesh configuration
93

Figure 9-3 Fulcrum FN2224 in a blade server
94

Figure 10-1 PMC-Sierra’s RSE-160 architecture
99

Figure 10-2 PMC-Sierra RSE-160 system design for an ATCA chassis
100

Figure 11-1 Tundra Tsi578 architecture
105

Figure 11-2 Media gateway using the Tundra Serial RapidIO switches
106

Figure 12-1 Enigma HybriCore fabric in a 640Gbps configuration
112

Figure 12-2 Erlang Xe system design
117

Figure 12-3 Mercury MC432 system design
123