| Figure
1-1. |
Typical
LAN architecture |
2 |
| Figure 1-2. |
Typical data-center components |
6
|
| Figure 2-1. |
IEEE 802 standards |
10 |
| Figure 2-2. |
IEEE 802.3 basic
frame format |
11 |
| Figure 2-3. |
Ethernet physical
layer |
13 |
| Figure 2-4. |
10G Ethernet physical
layer |
15 |
| Figure 2-5. |
Optical module size, power, and estimated price |
19 |
| Figure 3-1. |
Transmitted data eye (left) and received data eye (right) |
29 |
| Figure 3-2. |
Transmitted eye with pre-emphasis and received (right) eye |
32 |
| Figure 3-3. |
Impulse response and equalization |
33 |
| Figure 3-4. |
Conceptual phase-locked loop |
34 |
| Figure 4-1. |
Block diagram of typical GbE switch |
38 |
| Figure 4-2. |
Single-port GbE PHY simplified block diagram |
41 |
| Figure 4-3. |
Architecture of optical module |
43 |
| Figure 4-4. |
10Gbps serdes architecture |
45 |
| Figure 4-5. |
Generic block diagram of a 10GBase-T PHY |
46 |
| Figure 4-6. |
Circadiant tester results for 10GBase-LRM |
47 |
| Figure 5-1. |
10GbE switch forecast,
2005–2010 |
56 |
| Figure 5-2. |
Merchant Ethernet chip revenue (millions of dollars) |
60 |
| Figure 5-3. |
GbE switch and PHY revenue
share, 2005–2006 |
61 |
| Figure 6-1. |
Broadcom 48xGbE+2x10GbE stackable Layer 3 switch |
67 |
| Figure 7-1. |
LSI 48xGbE+2x10GbE managed Layer 3 switch |
80 |
| Figure 8-1. |
Marvell 48xGbE+2x10GbE stackable Layer 3 switch |
86 |
| Figure 10-1. |
Vitesse 24xGbE stackable Layer 2 switch |
98 |
| Figure 12-1. |
Simplified block diagram
of Solarflare’s 10Gbps PHY |
131 |
| Figure 13-1. |
Power-over-Ethernet wiring |
131 |
| Figure 13-2. |
PSE power-controller block diagram |
131 |
| Figure 13-3. |
PD power-controller block diagram |
131 |