| Figure
1-1. |
Typical
LAN architecture |
2 |
| Figure 1-2. |
Typical data-center components |
5 |
| Figure 1-3. |
Generic network architecture |
7 |
| Figure 2-1. |
IEEE 802 standards |
13 |
| Figure 2-2. |
IEEE 802.3 basic
frame format |
14 |
| Figure 2-3. |
VPLS switch conceptual model |
21 |
| Figure 2-4. |
Hierarchical traffic management |
23 |
| Figure 2-5. |
Ethernet physical layer |
24 |
| Figure 2-6. |
10G Ethernet physical layer |
26 |
| Figure 2-7. |
Layer model for 40G/100G Ethernet |
28 |
| Figure 2-8. |
Optical module size, power, and estimated price |
32 |
| Figure 3-1. |
Transmitted data eye (left) and received data eye (right |
39 |
| Figure 3-2. |
Transmitted eye with pre-emphasis (left) and received eye (right) |
42 |
| Figure 3-3. |
Impulse response and equalization |
43 |
| Figure 3-4. |
Conceptual diagram of a phase-locked loop |
44 |
| Figure 4-1. |
Block diagram of a typical GbE switch |
48 |
| Figure 4-2. |
Single-port GbE PHY simplified block diagram |
53 |
| Figure 4-3. |
Architecture of a generic optical module |
54 |
| Figure 4-4. |
10Gbps serdes architecture |
55 |
| Figure 4-5. |
Block diagram of a generic 10GBase-T PHY |
57 |
| Figure 4-6. |
Circadiant tester results for 10GBase-LRM |
59 |
| Figure 5-1. |
Forecast for Ethernet switch chips, 2008–2013 |
71 |
| Figure 5-2. |
Forecast for 10G Ethernet switch chips, 2008–2013 |
72 |
| Figure 5-3. |
Forecast for 10G Ethernet PHY shipments, 2008–2013 |
74 |
| Figure 5-4. |
Merchant Ethernet switch-chip revenue by speed, 2007–2008 |
76 |
| Figure 5-5. |
Gigabit Ethernet switch-chip and PHY market share, 2007–2008 |
77 |
| Figure 6-1. |
Broadcom 48xGbE+2x10GbE stackable Layer 3 switch |
84 |
| Figure 6-2. |
Broadcom Core XGS chip set in a data-center switch |
89 |
| Figure 7-1. |
Block diagram of Marvell 48xGbE+2x10GbE Layer 3 switch |
101 |
| Figure 9-1. |
Vitesse 24xGbE stackable Layer 2 switch |
111 |
| Figure 10-1. |
Centec 48xGbE+4x10GbE Carrier Ethernet switch design |
117 |
| Figure 10-2. |
Ethernity Carrier Ethernet application |
126 |
| Figure 10-3. |
Fulcrum FM4000 in a two-stage fat-tree architecture |
133 |
| Figure 10-4. |
Block diagram of Xelerated AX340 architecture |
141 |
| Figure 10-5. |
Xelerated AX340 in 16-port GPON line card |
142 |
| Figure 11-1. |
Plato 10GbE PHY architecture with analog signal processing |
163 |