A Guide to Network Processors, Ninth Edition
     
List of Figures
       
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Figure 1-1. Generic network architecture
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Figure 1-2. Wireline access networks
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Figure 1-3. 3GPP Release 5 IP-based cellular network architecture
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Figure 2-1. OSI layer traversal example
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Figure 2-2. Layer 2 protocol stacking within DSL network
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Figure 2-3. ATM protocol stack
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Figure 2-4. MPLS encapsulation
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Figure 2-5. Control and data planes
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Figure 2-6. RSVP host and router implementation
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Figure 2-7. Hierarchical traffic-management based on DSL Forum TR-059
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Figure 2-8. Standard line-card interfaces
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Figure 3-1. Block diagram of typical NPU
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Figure 4-1. NPU performance segments by revenue
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Figure 4-2. Preliminary 2007 NPU market share by revenue
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Figure 4-3. NPU market forecast through 2011
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Figure 5-1. AMCC nP37x0 block diagram
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Figure 5-2. AMCC OC-48 line card
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Figure 6-1. Bay Chesapeake block diagram
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Figure 6-2. Bay Chesapeake NPU in a 24xGbE+2x10GbE switch
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Figure 6-3. Bay Chesapeake NPU in a 2x10GbE line card
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Figure 7-1. Broadcom BCM88020 block diagram
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Figure 7-2. Broadcom 2x10GbE metro-Ethernet line card
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Figure 7-3. Broadcom StrataXGS III 24xGbE+2x10GbE metro-Ethernet switch
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Figure 8-1. EZchip NP-3 block diagram
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Figure 8-2. EZchip NP-3 line card
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Figure 9-1. LSI APP650 V2 block diagram
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Figure 9-2. LSI APP650 line card
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Figure 9-3. LSI APP3300-based base-station network interface
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Figure 10-1. Netronome NFP3200 block diagram
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Figure 10-2. Netronome NFP3200 10GbE line card
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Figure 11-1. Wintegra WinPath2 block diagram
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Figure 11-2. Channelized OC-3/12 line card based on WinPath and UFE
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Figure 11-3. Integrated IP DSLAM line card using WinArrow2
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Figure 11-4. WiMax base station using WinMax
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Figure 12-1. Xelerated PISC architecture
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Figure 12-2. Xelerated X11 block diagram
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Figure 12-3. Xelerated 2x10GbE line card with Dune FAP20V TM
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Figure 13-1. Ethernity ENET3000 IP DSLAM line card
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Figure 13-2. Lightstorm 10xGbE metro Ethernet switch
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Figure 13-3. Integrated IP DSLAM line card based on Mindspeed TSP3
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Figure 13-4. TranSwitch Diplomat-IP DSLAM
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