A Guide to Network Processors
Tenth Edition
     
List of Figures
       
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Figure 1-1. Generic network architecture
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Figure 1-2. Wireline access networks
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Figure 1-3. 3GPP Release 5 IP-based cellular network architecture
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Figure 2-1. OSI layer traversal example
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Figure 2-2. Layer 2 protocol stacking within DSL network
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Figure 2-3. ATM protocol stack
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Figure 2-4. MPLS encapsulation
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Figure 2-5. VPLS switch conceptual model
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Figure 2-6. Control and data planes
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Figure 2-7. Hierarchical traffic-management based on DSL Forum TR-059
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Figure 2-8. Standard line-card interfaces
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Figure 3-1. Block diagram of typical NPU
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Figure 4-1. NPU revenue by application segment, 2008
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Figure 4-2. NPU revenue by performance segment, 2006–2008
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Figure 4-3. NPU market share by revenue, 2008
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Figure 4-4. NPU market forecast, 2007–2013
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Figure 5-1. Bay Chesapeake block diagram
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Figure 5-2. Bay Chesapeake NPU in a 24xGbE+2x10GbE switch
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Figure 5-3. Bay Chesapeake NPU in a 2x10GbE line card
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Figure 6-1. Broadcom BCM88025 block diagram
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Figure 6-2. Broadcom 2x10GbE metro-Ethernet line card
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Figure 7-1. EZchip NP-3 block diagram
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Figure 7-2. EZchip NP-3 in a 10GbE line card
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Figure 8-1. LSI APP650 V2 block diagram
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Figure 8-2. LSI APP650 line card
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Figure 8-3. LSI APP3300-based base-station network interface
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Figure 9-1. Netronome NFP3200 block diagram
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Figure 9-2. Netronome NFP3200 10GbE line card
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Figure 10-1. Wintegra WinPath2 block diagram
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Figure 10-2. Channelized OC-3/12 line card based on WinPath2 and UFE
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Figure 10-3. Integrated IP DSLAM line card using WinArrow2
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Figure 10-4. WiMax base station using WinMax
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Figure 11-1. Xelerated PISC architecture
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Figure 11-2. Xelerated HX330 simplified block diagram
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Figure 11-3. Xelerated 4x10GbE line card with Dune fabric
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Figure 12-1. AMCC OC-48 line card
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Figure 12-2. Centec 48xGbE+4x10GbE Carrier Ethernet switch design
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Figure 12-3. Lightstorm 10xGbE metro Ethernet switch
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