| Figure 1-1. |
Firewalls and
the DMZ |
8 |
| Figure 2-1. |
Header and trailer
format for ESP tunnel mode |
21 |
| Figure 3-1. |
Block diagram of generic integrated security processor |
30 |
| Figure 3-2. |
Example of bit
permutation in the DES algorithm |
32 |
| Figure 3-3. |
Typical system
configuration with lookaside VPN/SSL processor |
33 |
| Figure 3-4. |
Typical curve
of IPSec performance versus packet size |
36 |
| Figure 4-1. |
Security-accelerator market share by revenue |
49 |
| Figure 5-1. |
Cavium Octeon CN58xx block diagram |
55 |
| Figure 5-2. |
Integrated security appliance based on Cavium Octeon Plus |
56 |
| Figure 5-3. |
Freescale MPC8572 block diagram |
61 |
| Figure 5-4. |
Mistletoe VF processor conceptual block diagram |
69 |
| Figure 5-5. |
Block diagram of P.A. Semi's PWRficient 1682M processor |
71 |
| Figure 5-6. |
RMI XLR processor block diagram |
76 |
| Figure 5-7. |
Security appliance design based on RMI XLR |
77 |
| Figure 6-1. |
Broadcom BCM5825 block diagram |
86 |
| Figure 6-2. |
Cavium Nitrox II CN2800 block diagram |
89 |
| Figure 6-3. |
Cavium Nitrox II CN2800 IPSec flow-through system diagram |
90 |
| Figure 6-4. |
Hifn 8450 block diagram |
96 |
| Figure 6-5. |
SafeNet SafeXcel-184x block diagram |
100 |
| Figure 7-1. |
Tarari Grand Prix 7000 block diagram |
111 |