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Linley Tech Seminar: High-Speed Interconnects
May 14, 2008
DoubleTree Hotel, San Jose, CA
Seminar:
9:00 - 3:45 pm
Reception, exhibits, and raffle immediately following
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8:15 |
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9:00 |
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Continental breakfast and registration |
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9:00 |
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9:45 |
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Session
1: Interconnect Trends and Standards
Jag
Bolaria,
senior analyst at The Linley Group, will present
an overview of interconnect technology, standards,
and silicon trends. These will include PCIe, RapidIO, HyperTransport, Display Interfaces, and Ethernet at 10Gbps and beyond. |
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9:45 |
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12:00 |
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Session
2: System Interconnects
This
session will describe
how leading system level interconnects such as PCIe
and
RapidIO
can
be used
in different applications
and what advantage each provides to the system designer. |
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PCI Express Gen-II Signal Conditioning and PC Graphics Switching Solutions
Shaf Rahman, Sr. Director of Marketing, Switch and Interface Products,
Pericom Semiconductor
This presentation will discuss signal conditioning for PCI Express Gen-II, SAS and e-SATA interconnects for servers and PC Computing systems. The presentation will also cover high-speed switching between PC graphics and monitors/TVs based on PCI Express Gen-II and DisplayPort (DP) architectures.
In a World of Complex System-on-Chip Devices, are System Interconnects Still Needed?
Greg Shippen, System Architect, Freescale
External system-level interconnects are and have been key to constructing large systems out of relatively simple single-function devices. Recently, complex multicore System-on-Chip (SoC) devices have emerged with on-chip cross-bar fabrics interconnecting processor cores and accelerator functions. What impact does this trend have for external interconnects? Are some interconnects better able to leverage this trend than others? This presentation examines these questions as well as the trade-offs for selecting the optimum external interconnect.
RapidIO: The Embedded System Interconnect of Choice
Stephane Gagnon, Director of Strategic Marketing, Tundra
Applications such as wireless base stations, video processing infrastructure, radar signal processing, military, and medical applications all require the use of multiple DSP and/or processors within a single system. Serial RapidIO is the optimal interconnect for processor communication in a true peer-to-peer environment, and allows inter-processor messaging with the low latency and high bandwidth that designers require, both chip-to-chip or across the backplane.
This presentation will review system architectures implemented with Serial RapidIO and discuss system interconnect scalability, flexibility, and software investment protection.
Designing 10Gbps Applications on Xilinx Virtex-5 Platforms
Navneet Rao, Connectivity System Architect, Xilinx
10Gbps applications are here today. OEMs are deploying systems to cater to the information explosion driven by convergence of voice, video, and data applications. Of primary importance is the choice of the data transport architectures to meet the stringent demands for bandwidth, latency and performance. This presentation will address scenarios and tradeoffs for designing with FPGAs using PCI Express, Serial RapidIO, XAUI, Ethernet, and other proprietary protocols. Also discussed will be key optimization and implementation strategies when designing the latest Xilinx Virtex-5 LXT/SXT/FXT platforms. |
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There will be a Q&A session after each talk. |
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12:00 |
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1:00 |
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Gourmet lunch, hosted speaker tables,
and exhibits |
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1:00 |
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2:40 |
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Session
3: 10Gbps Ethernet and Beyond
This session will examine 10Gbps Ethernet PHY devices for optical and copper cabling. The session also looks at next generation technologies beyond 10GbE. |
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Migrating LANs from 1Gbps to 10Gbps
Jose Tellado, Co-Founder and Vice President, Systems Engineering, Teranetics
Teranetics will provide an overview of 10GBASE-T technology and show how it can enable substantial increases in LAN networking capabilities in the data center. We compare data handling capabilities of networking equipment based on 10GBASE-T with those of networking equipment based on 1000BASE-T in terms of throughput, density, cost per gigabit and other general metrics of interest.
Ethernet Backplane Connectivity on 10GBase-KR and Beyond for 100Gbps Systems
Subhash Roy, CTO, Transport Products, AMCC
Aggregation requirements within the network and increased computing power in the data center are driving the need for 10Gbps ports. In modular systems, these 10Gbps ports need to be connected through a high-speed backplane. This presentation will focus on the issues and tradeoffs for building next-generation equipment where backplane connectivity needs to scale to 10GbE and beyond.
SFP+: The 10GbE Game Changer
John O'Neill, VP Marketing, ClariPhy
This presentation will present a retrospect of the 10GbE optical market and explore future scenarios where the 10GbE market expands rapidly while simultaneously remaining nearly exclusively SFP+ based.
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There will be a Q&A session after each talk. |
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3:45 |
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Session
4: Choosing the Right Interconnect
This closing panel, moderated by Jag Bolaria, will
focus on the relative strengths and positioning of leading
interconnects. In addition to giving the audience an opportunity to ask questions, this session will address the changes expected in the leading interconnects. It will also look at the implementation challenges of using these interconnects.
Moderator:
Jag Bolaria, The Linley Group
Panelists: Navneet Rao, Xilinx; Jose Tellado, Teranetics; Subhash Roy, AMCC; John O'Neill, ClariPhy
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3:45 |
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4:45 |
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Reception
with Exhibits and Raffle.
View the exhibits, network with the speakers, your colleagues, and our analysts while you nosh on some delicious food and drink. As a special bonus, we'll be giving away an Apple iPod as well as one of The Linley Group's reports. How can you go wrong?
(Must be present to win.)
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Program
is subject to change without prior notice. Last updated:
May 8, 2008 |
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Registration:
You can either register
online or download this form ,
complete it, and fax it to us at 1.650.745.1490.
Qualified
attendees are eligible for free admission if registered
by May 9. Registration for non-qualified attendees is $495 if received by that date. Registrations received after May 9,
or at the door,
will
be $125
for qualified attendees and $595
for non-qualified attendees. We
reserve the right to determine attendee qualification or to
refuse admission to any person.
The
seminar is targeted at OEMs, board developers, software developers, press, and the financial community.
Information
collected for this event will be shared with the sponsors
paying for this seminar. This information will not be
shared with companies other than the sponsors of this
event.
Further
questions? Contact The Linley Group:
Phone: 1.800.413.2881 (toll free in US) or 1.408.281.1947 or email: customer
service |
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© 2002-2008 The Linley Group

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