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CPU Cores and IP for Networking
Held March 19, 2008

Are you using or evaluating intellectual property (IP) for your ASIC or SoC (systems on a chip) device designs? If so, you might want to download the proceedings from our March 19 Linley Tech seminar on CPU cores and other licensable intellectual property (IP) for networking and communications applications. This one-day event covered the latest technology trends, tips, and traps in using and understanding the IP blocks available from leading vendors.

We had an outstanding lineup of technical presenters, including:

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The Linley Group's Principal Analyst, Linley Gwennap, will provide a CPU and IP Overview
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IBM Senior Engineer Harry Linzer will present "Building a Single-Chip Control/Data Plane"
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SafeNet Systems Engineering Manager Steve Singer will present "How Application Requirements Drive Security Architecture"
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IPextreme CEO Warren Savage will present "Licensing Freescale's Power Architecture and ColdFire Technologies"
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Tensilica Principal System Architect Jerry Redington will present "Networking Applications for Xtensa Configurable Processors"
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T-RAM CTO Farid Nemati will present "Thyristor RAM: A Novel Embedded-Memory Technology"
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MIPS Director of Engineering Vidya Rajagopalan will present "Accelerating Networking Functions Using MIPS32"
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ARM Director of CPUs Nandan Nayampally will present "Evaluating Multicore Tradeoffs for SMB Networking"
> Synopsys Director of Product Marketing Navraj Nandra will present "Designing High-Speed Transceivers"
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Shay Gal-On, Director of Software Engineering, EEMBC, will present "Analyzing Multicore and Networking Processor Performance"

The seminar was intended for designers of networking or communications ASICs or SoC products that use licensed intellectual property, including designers at equipment companies or semiconductor vendors. The program provided information on the newest IP products as well as how to evaluate, integrate, configure, and program these IP cores for applications similar to the ones they are designing.

Event sponsors: Freescale, IBM, SafeNet, Tensilica, T-RAM, and EEMBC.

Detailed program

Proceedings Registration







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