CPU Core and IP for Networking

Held March 19, 2008

Session 1: CPU and IP Overview
      Linley Gwennap, Principal Analyst, The Linley Group

This session will discuss the advantages and disadvantages of licensing IP for ASIC and system-on-a-chip (SoC) designs. He will quickly review the different types of IP available for networking and communications applications. He will close with an overview of CPU technology, with an emphasis on the key features used to compare licensable CPU cores..

Session 2: Coprocessor and Interface IP for Networking
Moderated by Joseph Byrne, Senior Analyst, The Linley Group

Licensed IP enables designers to incorporate in their chips specialized functions for which they lack the time or expertise to develop and validate independently. Some functions, such as encryption, offload complex operations from a CPU. Other functions, such as high-speed I/O and radios, enhance the connectivity of a system-on-a-chip (SoC) using mixed-signal design.

How Application Requirements Drive Security Architecture
      Steve Singer, Systems Engineering Manager, SafeNet

Today, applications are driving security needs and inspiring the best security solutions. This presentation discusses how security is handled for various applications, including where in the system security is implemented, and how it fits into the overall system architecture.

Designing High-Speed Transceivers
      Navraj Nandra, Director of Product Marketing, Synopsys

Combining high-speed digital and analog circuits, transceivers have always been a challenge to design. Increasing line speeds and port densities of communications equipment require correspondingly faster board and backplane interconnect, further increasing the design challenge of transceivers. CMOS processes at 65nm and smaller present additional difficulties. This presentation discusses designing the analog side of a PHY and the various physical effects caused by deep-submicron processes.

Thyristor RAM: A Novel Embedded-Memory Technology
      Farid Nemati, CTO, T-RAM

This presentation will introduce Thyristor-RAM technology as a compelling solution for high-performance high-density embedded memory, particularly for networking, telecomm, and computation SoCs. In standard CMOS, Thyristor-RAM macros match 6T-SRAM in performance and standby power while providing 2.5x better density and 2x better active power.

This presentation will highlight EEMBC’s multicore benchmark strategy, using data obtained from actual processor tests to show how various workload combinations affect performance in multicore designs. The goal is to determine CPU, memory, and operating system bottlenecks. The presentation will also show requirements for testing the performance of next-generation SoCs in networking and communications applications.

Session 4: CPU Cores for Networking
      Moderated by Linley Gwennap, Principal Analyst, The Linley Group

Licensable CPU cores are far from a commodity. In this session, leading vendors describe the unique features of their CPUs and how these features can improve efficiency and performance in various networking and communications applications.

Licensing Freescale’s Power Architecture and ColdFire Technologies
      Warren Savage, CEO, IPextreme

Together with IPextreme, Freescale has opened up licensing of its leading ColdFire and Power Architecture CPUs so that companies can combine their own designs with Freescale technology in the form of licensable IP cores. This presentation will describe these licensable IP cores and the ecosystems available to companies producing networking products.

Building a Single-Chip Control/Data Plane
      Harry Linzer, Senior Engineer, IBM

45nm and 32nm technologies enable massive system consolidation.  For the first time, an array of network-connected function and processing engines can be combined in a cost-competitive, low-power, single-chip control/data plane.  This presentation will address the challenges of delivering such a solution, from the integration of different CPU micro-architectures and processing engines to the analysis and thorough engineering needed to ensure near-100% availability.

Networking Applications for Xtensa Configurable Processors
      Jerry Redington, Principal System Architect, Tensilica

Tensilica’s Xtensa CPUs are used in a wide range of networking and communications applications. This presentation will provide examples of how one or more designer-extended Xtensa CPUs can implement networking protocols in a programmable, efficient, and high-performance manner.

Evaluating Multicore Tradeoffs for SMB Networking
      Nandan Nayampally, Director of CPUs, ARM

As multicore designs become more common, the method of coupling the powerful CPU subsystem to the remainder of the SoC is a critical hardware and software challenge. This presentation will enumerate key design considerations and then examine multiple networking applications to highlight the advantages and disadvantages of different multicore configurations.

Accelerating Networking Functions Using MIPS32
       Vidya Rajagopalan, Director of Engineering, MIPS

Designers of networking chips are increasingly challenged to integrate more and more disparate functions, such as traffic management, QoS, and other protocols. This presentation will discuss key elements and use models of the MIPS32 architecture that address some of today’s challenges in designing SoCs for networking applications such as VoIP, residential gateways, and home routers.