Session 1: Processor Overview

Linley Gwennap, principal analyst at The Linley Group, presented an overview of high-speed embedded processor design. He also highlights technology trends and provides market share and forecast data.

Session 2: Multicore Microprocessors

This session, moderated by Linley Gwennap, explored the newest multicore processors for data-plane and control-plane applications. These processors include networking interfaces and function units to optimize the analysis and processing of data packets as well as multiple high-speed CPU cores.

Market Drivers and Enabling Technologies for Multicore Processors
   Toby Foster, Product Marketing Manager, Freescale

Multicore processors provide flexibility for integration of control and packet processing in network system designs. Designs that must be scalable can no longer rely on shared single system resources. New user models are emerging and multiported designs are required to handle the new challenges of scale and concurrent processing operations. Hardware assists and virtualization of resources are needed to process multiple requests in real time and to manage multiple operating systems. This presentation reviews how system solutions must account for extended life cycles, extreme operating temperature ranges and balance the need for very low power consumption with high performance. It also provides the first public disclosure in North America of a new multicore processor from Freescale.

Next-Generation Control-Plane and Data-Plane Processors for 3G/4G Mobile Infrastructure
    Sunil Kar, Director of Communications Processor Strategy, RMI

Multicore, multithread processors provide the features, performance, and programmability to meet the challenges of 4G mobile networks. The emerging paths to 4G (LTE, WiMAX, etc.) have shrunk the network topology, using a flattened architecture and IP-based transport between the network elements. The base stations for 4G need significantly higher packet processing and low, deterministic latency within a stringent power budget. Beyond packet processing, there is also the need for ciphering, header compression, and other higher-layer processing. In the network core, the network elements need to handle high-throughput packet traffic, while providing protection against emerging security threats and packet intelligence for service provisioning and session management. This presentation explores the application of a next-generation multi-core processor based on a high-performance CPU that provides the features, performance, and programmability to meet the challenges of control-plane and data-plane processing for 4G mobile-infrastructure platforms.

A Deterministic Multicore Architecture for Communications Applications
   David Sonnier, Fellow and Chief Product Architect, LSI

In this presentation, LSI outlines an innovative approach to designing multicore processors targeted for the communication space, providing the first public disclosure of a future multicore architecture from LSI. Multicore architectures are in the process of constant evolution. First-generation designs focused on applying a compute-centric model to the packet-processing problem. Attempting to solve the software issues that haunted traditional network processors, chip-designers introduced new problems such as a lack of determinism. A new generation of multicore processors is emerging to combine dataplane and control-plane processing in a highly deterministic design while providing a software paradigm that fits the application-development model. The building blocks for this multicore processor architecture (CPU, DSP, offload engines, communication infrastructure) are discussed along with how these blocks can be used to meet the requirements of the rapidly changing communication space.

Octeon Architecture Optimization
   Kin-Yip Liu, Sr. Director of Field Application Engineering, Cavium Networks

Cavium’s Octeon processors integrate 1 to 16 enhanced MIPS64 CPU cores and a comprehensive set of hardware accelerators to maximize application performance, maximize power efficiency, achieve linear multicore scaling, and minimize processing latency. This presentation details the Octeon architecture and illustrates the advantages of the architecture in key applications.

Session 3: Embedded Software

This session, moderated by Joseph Byrne of The Linley Group, examined the ecosystem for multicore processors, discussing embedded software available to OEMs to derive the most value from these chips.

Optimizing Packet-Processing Architectures for Highest Performance
   Mike Coward, CTO and co-founder, Continuous Computing

Multicore processors have tremendous latent potential for packet processing, but harnessing this potential requires specific system-level design optimizations. Designing a packet-processing subsystem using a multicore processor requires careful choice of coprocessors and use of board-level interconnect. Software must be designed with multithreading in mind for the subsystem to take full advantage of the potential of multicore processors. This presentation discusses the tradeoffs of coupling packet-processors with external search engines, selecting on-chip bussing schemes, and optimizing software for multicore processors.

A System-Level Approach to Multicore Software
   Magnus Gille, System Software Engineer, Enea

Multicore processors deliver new capabilities in terms of scalability, provisioning, power management, and configurability but require a new software infrastructure to take full advantage of these capabilities. In this presentation, Enea discusses its system-level approach to transitioning developers from single-core to multicore architectures. Topics discussed include hybrid/heterogeneous operating-systems environments, hypervisor solutions for rapid provisioning and shared-resource management, power management, and a new category of software called data-plane management. In the course of the presentation, a system-level approach to connecting the network-management layer to the deepest device-management capabilities.

The Embedded Linux Supply Chain
   James Ready, CTO, MontaVista Software

The embedded Linux market has undergone a shift. In recent years, the large semiconductor vendors have become providers of embedded Linux technology. This changes the embedded Linux supply chain and requires both developers and vendors to take a new approach to embedded Linux development. In this session we’ll discuss the importance of having an aligned embedded Linux supply chain and the resulting benefits.

Session 4: Broadband-Gateway Processors

This session, moderated by Joseph Byrne, examined processors used to provide broadband access.

Processing in the Gigabit Broadband Era
   Victor Simileysky, Principal MTS, TranSwitch

With the deployment of higher bandwidth broadband access technologies, such as passive optical networks (PON), IEEE 802.11n Wi-Fi, and 3G/4G wireless, and the rollout of triple- and quad-play services, end-user demand for bandwidth has increased markedly, from tens to hundreds of megabits. This increase in demand for bandwidth has spurred the industry to introduce a new generation of communications processors that support packet processing at gigabit rates. This presentation identifies the features that these processors must support to meet these new bandwidth demands while simultaneously complying with seemingly conflicting requirements for reduced power consumption and bill-of-materials (BOM) cost.

There was Q&A after this talk.

Performance Requirements for Home Gateways
   Duncan Bees, CTO, Home Gateway Initiative

Broadband networks are delivering more bandwidth to residential customers, but they are also delivering new services. Besides web and email data, these services include HD video, VoIP, peer-to-peer data, and cellular backhaul from femtocells. Supporting these services, with their individual requirements for bandwidth and tolerance of latency, and the higher data-transfer rates requires processors that are not just fast at computing but that are also able to classify multiple flows, apply QoS, and handle gigabit-speed interfaces. This presentation discusses key system-level metrics for home gateways and the performance-evaluation model of the Home Gateway Initiative.

Session 5: Panel: Understanding Processor Performance

In this session, Markus Levy, president of the Embedded Microprocessor Benchmark Consortium and the Multicore Association, hosted a forum of processor experts from leading OEMs to discuss processor-performance issues. Panelists include:

• Duncan Bees, CTO, Home Gateway Initiative
• Alex Bachmutsky, Chief Architect, Nokia Siemens Networks
• Nikhil Jayaram, Director of Engineering, Cisco
• John Gmuender, VP of Engineering, SonicWall

The conference was intended for OEMs, ODMs, network-equipment vendors, network service providers, system designers, software developers, press, and the financial community.

Information collected for this event will be shared with the sponsors paying for this seminar. This information will not be shared with companies other than the sponsors of this event.

Further questions?   Contact The Linley Group:
Phone: 1.800.413.2881 (toll free in US) or 1.408.281.1947 or email: customer service