Session 6: Architecture Ecosystem

Key Features of the Power Architecture
   Brad Frey, Power Architecture Advisory Council Chair, Power.org/IBM

Used in PowerQuicc and QorIQ processors from Freescale as well as PowerPC processors from IBM and AMCC, the Power architecture has numerous features making it well suited to next-generation processors. This presentation provides an overview of Power, including a description of the instruction-set architecture, support for multicore and virtualization, software-development tools, and the open and collaborative Power.org community.

Session 7: Processor Cores

This session, moderated by Joseph Byrne of The Linley Group, explored the design and use of processor IP.

No Assembly Required: Enabling C Programmers to Exploit the Parallelism Inherent in Today's Architectures
   Steve Cox, VP of North America Operations, Target Compiler Technologies

Too often, processor architects create novel techniques for efficient computation, only to find that in order to exploit the efficiencies, critical sections of code must be painstakingly crafted in assembly. The problem is two-fold. First, getting rapid insight into the “compiler-friendliness” of specific architectural innovations is generally limited to companies that have an in-house compiler development team. Second, even in that case, common compiler starting points (e.g., gcc) are ill suited to exploiting the specialization and parallelism that embodies the architectural innovation. This presentation describes a processor design tool-suite that addresses both of these issues, enabling the benefits realized when the performance of highly specialized architectures can be exploited directly from C.

Dynamic Behavior of Parallel Programs and Data Race Detection
   David Lau, Director of Architecture, MIPS Technologies

Detecting data race conditions in a parallel program is a two-step process. The first step is to trace the program’s dynamic behavior in terms of synchronization flow and data accesses using either software instrumentation or, when available, hardware trace capabilities. The second stage is to analyze the traces using various heuristics and identify potential or actual races. This talk reviews the most promising dynamic behavior analysis technologies and their potential for detecting concurrency errors like data races.

Introduction to the New High-Performance IBM PowerPC Core
   Bryan Talik, Engineering Director of PowerPC Cores Development, IBM

The IBM 4xx series of PowerPC cores has satisfied embedded applications for more than a decade. To expand the range of these offerings, IBM is introducing a new IBM PowerPC processor core. This new high-end 4xx core is designed to meet or exceed the demands of current and future high-performance single or SMP embedded applications. In this presentation, IBM provides an architectural overview of the new CPU and illustrates how the core’s features satisfy the needs of high performance/low power embedded applications.

Session 8: Key Function Units in Multicore Processors

This session, moderated by Linley Gwennap, examined how hardware function units complement CPU cores to enable multicore processors to efficiently handle embedded-processing tasks.

Multicore Processor Cache and Subsystem Design for a High-Performance PowerPC Targeting Networking and Storage
   Wayne Nation, Distinguished Engineer, LSI

IBM and LSI have joined forces to create the next-generation PowerPC core and its multicore subsystem. As part of this collaboration, LSI contributed to the L2 cache design that connects the processor core and IBM’s next generation multicore interconnect, PLB6. The interconnect architecture defines L2 cache and peripheral interfaces, commands, and protocol rules that support a range of high-performance implementations. This presentation describes the L2 cache architecture, its coherency protocol, and features of the processor subsystem. LSI is including the new CPU core and L2 cache in its networking and storage products.

Queuing and Traffic Management requirements in Next Generation SoCs
   Satish Sathe, SoC Architect, AppliedMicro (AMCC)

Next generation systems-on-chip (SoC) are increasingly made up of multiple processors, network and system interfaces, and purpose-built accelerators. These diverse elements need special queuing and traffic management capabilities to ensure optimal performance, fault isolation, and fair sharing while providing a simple programming interface. This presentation will focus on the benefits that queuing and traffic management can bring to SoCs.

Session 9: Processing and Security

This session, moderated by Joseph Byrne of The Linley Group, explored semiconductors used in conjunction with embedded processors to maximize performance on networking applications.

Removing barriers Between Multicore, Security Processing and NPU Designs
   Kurt Parker, FAE, Netronome

Network processors are specialized packet processors optimized for fixed-function packet (L2-L3) forwarding, while general-purpose multicore CPUs are ideal for higher layer (L4-L7) processing. To address the growing need for intelligent packet processing consisting of both header and content processing at 20Gbps, a processor is needed that can handle millions flows, packet processing, security acceleration, deep packet inspection (DPI), and IO Virtualization (IOV). This talk discusses these challenges and how the Netronome NFP-32xx addresses them.

Building Trust in Your Network Infrastructure Using Secure Platform Solutions
   Steve Singer, Worldwide Systems Engineering Manager, SafeNet

Data security and platform security are converging. Data security is the protection of data as it is stored or transported and is traditionally integrated with NPUs or data-plane ASICs. Platform security is concerned with the integrity and security of the systems that process the data and has been handled by general-purpose processors. The importance of platform security is increasing as application processing is added to network elements, prompting the need for implementation options ranging from a software-only setup to a fully standalone hardware module. Similarly, the typical cryptography accelerators found in networking security are taking on packet classification and forwarding functions. This presentation discusses how equipment and semiconductor vendors can use SafeNet’s Secure Platform and Packet Engine solutions to address both data and platform security.

Implementing Security and Threat Management at Wire Speed with Multicore/Multithread Embedded Processors and Content Inspection Processors
   Dilip Ramachandran, Director of Communications Processor Solutions, RMI

Steadily increasing bandwidth and the growing sophistication of attacks is driving requirements for faster network-security processing. Security simultaneously is moving from a discrete function to one integrated with other functions, such as routing, presenting a greater load on the processors implementing the combined functions. This presentation explores the use of best-in-class multi-core, multi-threaded processors along with high-performance Layer 7 content processors to meet the increasing requirements of next-generation UTM, IPS/IDS and firewall security appliances.

Session 10: Single and Dual-Core Microprocessors

This session, moderated by Linley Gwennap, explored the newest high-speed embedded processors for communications applications.

A High-Performance, Low-Power CPU for Multiple Applications
   Sammy Tao, Sr. Product Line Manager, Marvell

The next billion intelligent consumer and embedded devices require low system BOM cost, high performance, and a rich software ecosystem. This presentation discusses the PXA168, which leads the latest generation of Marvell's processor lineup and includes an ARM and WMMX2 compatible core based on Marvell Sheeva technology, multimedia and 2D graphics acceleration, flexibility for memory types and Internet connectivity, a high degree of integration with peripherals such as Ethernet and PCIe, and Marvell Qdeo Intelligent Color Remapping. The combination of these provides flexibility to scale from embedded devices to consumer gadgets with advanced multimedia and easy-to-program user interfaces.

Meeting Energy Efficiency Standards With Innovative Energy Management Strategies in Embedded Processor SoCs
   Greg Shippen, System Architect, Freescale

Energy efficiency has become an important requirement across a wide range of applications in the embedded processor space. Freescale processor SoCs have recently introduced new energy management strategies that allow previously unachievable levels of energy efficiency without loss of important system functionality. This presentation briefly reviews market drivers for energy efficiency and then discusses various strategies to manage power within the constraints of today’s cost-efficient small form-factor designs with limited airflow.

A Very Low-power Processor for the Digital Home
   Kin-Yip Liu, Sr. Director of Field Application Engineering, Cavium Networks

Processors for the digital home must support high bandwidth connections and also securely deliver data, video, and voice services. These chips must also be cost-effective—integrating hardware acceleration, providing a variety of interfaces, and drawing little power. In this presentation, Cavium publicly discloses for the first time in North America technical details of a new processor optimized for high-volume FTTH gateways and digital-consumer systems, the Econa CNS3xxx.

The conference was intended for OEMs, ODMs, network-equipment vendors, network service providers, system designers, software developers, press, and the financial community.

Information collected for this event will be shared with the sponsors paying for this seminar. This information will not be shared with companies other than the sponsors of this event.

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