Processors for Networking and Communications

Held November 14, 2007

Session 1: Processor Architecture Overview

In this session, Linley Gwennap, principal analyst of The Linley Group, will provide an overview of high-speed embedded processor design. He will also highlight technology trends and provide data on market size and share.

Session 2: Processors for SMB/SOHO

This session, moderated by Joe Byrne of The Linley Group, explores the newest processors for the hot small/medium business (SMB) and small-office/home-office (SOHO) segments. These processors typically combine control-plane and data-plane functions, enabling the creation of low-cost gateways and appliances.

Processor Architecture for Communications and Media Processors
     David Fotland, CTO, Ubicom

Routers, digital media devices, and other systems within the connected digital home require increasing bandwidth, network processing, and media processing, yet they remain cost-sensitive. This presentation describes how the Ubicom32 architecture addresses these requirements through its networking-optimized instruction set, deterministic 10-way hardware multithreading, zero-overhead context switching, integrated fast-access on-chip memory, dedicated security engine, DSP extensions, and flexible software I/O.

Processors For Carrier-Grade Gateways for SMB and Remote/Branch Offices
     David Sonnier, Chief Architect for Networking, LSI

Service providers are increasingly offering new, revenue-generating services such as voice, video, and data (triple play), which are increasing requirements for intelligence, quality of service (QoS), security, control, and performance monitoring. This presentation will discuss these trends and explain how LSI’s Advanced Communication Processors meet these requirements, enabling low-cost integrated designs targeted at access infrastructure and customer premises equipment.

Enabling Embedded Secure Networked Applications Using SoC Platforms
     Sanjay Manney, Director, Microprocessor Products Division, PMC-Sierra

Requirements continue to evolve for embedded applications with secure IP connections, ranging from networking and storage to surveillance. The challenge for OEMs is to meet these evolving requirements while reusing hardware and software to reduce design time and cost. To address these challenges, this presentation will discuss a cost-optimized, high-performance SoC processor and the infrastructure to support it.

Dual-Core Processors for Carrier-Class SMB/SOHO Broadband Gateways
     Jim Johnston, CTO, Mindspeed Technologies

This presentation will describe a new family of dual-core processor SoCs designed to enable service providers to cost-effectively support sophisticated applications, high-performance packet processing and deterministic quality of service (QoS) for the triple-play broadband home and small and medium-sized enterprise (SME) markets. The Comcerto 100 Series of devices provides service providers the applications and performance headroom needed to deploy new revenue-generating services to broadband residential and SME subscribers.

Q&A and panel discussion featuring above speakers.

Session 3: High-Speed Embedded Processors

This session, moderated by Linley Gwennap, digs into the designs of leading-edge processors that can be used in enterprise, metro, and other demanding applications. These processors typically combine multiple powerful CPUs with accelerators and high-speed I/O to deliver the ultimate in high performance.

Network Convergence: Challenges and Promises of System-on-a-Chip
     Raj Singh, Communications Architect, IBM

The trade-off between performance and programmability is a perennial challenge faced by equipment designers for wireless access and core networks. This presentation will discuss evolving market dynamics, trends, and challenges, highlighting IBM’s system-on-a-chip (SoC) technology as a scalable, flexible platform to meet these market demands, and explain the potential of virtualization technology in addressing the demands of next-generation communications platforms.

Processor Architecture for All-IP Converged Networks
     Dan Bouvier, Process CTO, AMCC

The demands of evolving all-IP convergence in wired and wireless networks place new requirements on the underlying processing elements. This presentation will explore the "converged" processor needs including the processor complex, inter- and intra-chip communications, and the role of hardware assist and acceleration.

A High-Performance General-Purpose Processor Using 64 Cores
     Richard Schooler, VP of Software Engineering, Tilera

Rich services encompassing Layers 3 through 7 are being deployed throughout the modern business network; examples include intrusion prevention, spam filtering, and QoS provisioning. As network speeds increase from 1Gbps to 10Gbps, these new services create an enormous demand for compute power within networking switches, routers, load balancers, and security appliances. Tilera will discuss its recently announced TILE64 processor and the opportunities that an array of 64 processor cores on a single chip affords in designing high-performance and flexible networking products.

Multicore Processors for Networking and Communications
     Toby Foster, System Architect, Freescale

Dual-core processors have become the new workhorses in high-performance networking. This presentation will examine the optimization of CPU design, application offloads, memory subsystems, and high-speed packetized and non-packetized interfaces. It will also address actual usage cases, including the implications of symmetric and asymmetric multiprocessing models and the state of software availability.

A Dual-Core Power Processor for Networking Applications
     Mark Hayter, Chief System Architect, P.A. Semi

The presentation will describe P.A. Semi’s PWRficient PA6T-1682M processor, including its low-power features, I/O subsystem (protocol engine support, throughput, and latencies, offload engines), and memory-subsystem performance. In addition, it will discuss how the 1682M can support logical partitions and hardware separation, provide sample system-block diagrams, and show a detailed device power breakdown.

Q&A and panel discussion featuring above speakers.

Session 4: Closing Panel

Architectural trade-offs in processors for communications

Processor companies addressing communications applications have taken different approaches. Some suppliers rely on standard RISC CPUs for dataplane processing. Others use a full-fledged CPU architecture but one that’s proprietary and enhanced for communications processing. Finally, a third group supplements standard CPUs with specialized dataplane engines. This panel explores the tradeoffs of each approach and the applications where each approach is best suited.

Moderator: Joseph Byrne, The Linley Group
Panelists:   Toby Foster, Freescale; David Fotland, Ubicom; Dan Bouvier, AMCC; David Sonnier, LSI; and Richard Schooler, Tilera.

Request a free copy of the presentations by completing the registration form.

The seminar was intended for system designers, OEMs, network-equipment vendors, service providers, software vendors, press, and the financial community.

Information collected for this event will be shared with the sponsors paying for this seminar. This information will not be shared with companies other than the sponsors of this event.

Further questions?   Contact The Linley Group:
Phone: 1.800.413.2881 (toll free in US) or 1.408.281.1947 or email: customer service