Faster, Multithreaded CPUS VDSL, PON, and other high-speed broadband technologies require much more packet processing than traditional broadband. The simplest packet-processing architecture is a single CPU that handles all control- and data-plane tasks in software. A commodity RISC CPU (e.g., 200MHz MIPS 4K) can route about 25,000 packets per second, which translates to 100Mbps for average packets. When performing tasks that require more instructions per packet, such as firewall/NAT, the same CPU may achieve only 8,000 packets per second, cutting the performance to 30Mbps on average packets. Adding functions such as IPSec, ATM bonding, or quality of service (QoS) will further reduce throughput. Thus, for residential gateways operating at ADSL speed or 802.11b WLANs, a single commodity CPU is adequate. But for VDSL and PON, a commodity CPU starts to become a bottleneck. The popular MIPS 4K CPU, therefore, is being supplanted by faster CPUs. Some vendors are licensing the faster MIPS 24K or 34K, but Broadcom, Freescale, Intel, Marvell, and Ubicom design their own CPUs. To achieve greater utilization, companies are starting to use multithreading, which allows a single physical CPU to provide two or more threads, each of which appears to software as a separate processor. The CPU switches among the threads every cycle; if one thread is stalled due to a memory access or other slow operation, the CPU simply executes the other threads instead. This method improves CPU efficiency when separate tasks can be assigned to each thread. PMC, for example, assigns control-plane tasks to one thread, voice to another, and data-plane tasks to other threads. Broadcom and Ubicom also have multithreaded processors. Scaling Performance Even
with multithreading, increasing CPU performance to handle faster
data rates and more services would result in an expensive chip
that dissipates too much power. It is more efficient, instead,
to dedicate specialized resources for data-plane processing. The second step has been to use programmable packet engines, principally for Layer 3 and higher functions. Packet engines are optimized for net-working tasks and therefore use less die area and less power than a comparable CPU does. A packet engine is a vital complement to both CPUs and hardwired logic for gateways connected to networks at 100Mbps and faster. Because PON gateways have the highest data rates and deliver the most services, we find packet engines in PON controllers. They are also in the newest VDSL gateway processors. Dedicated hardware should yield better performance under combined heavy loads from control-plane, data-plane, and voice processing. VoIP Support Most gateway processors announced in the past year handle voice coding. How they implement the function, however, is changing. Earlier devices usually used a DSP, either integrated with the voice processor or attached externally. Now, most vendors use a CPU instead. Using a CPU for voice coding eliminates the die area required for a separate voice DSP. Developing voice software on a CPU is easier than on a DSP. Another advantage is that CPUs support unlimited code space through caching, whereas most DSPs have a fixed-size code store. As the number of voice codecs increases, this code store is often too small to hold them all. Recent gateway processors illustrate different approaches to CPU-based voice processing. Danube dedicates an entire CPU core to the task, reserving the chip’s other CPU for other tasks. Freescale simply runs the voice software on the main CPU, leaving it up to the operating system to ensure real-time response. Broadcom, PMC, and Ubicom dedicate a single thread to voice processing. CPU-based voice processing reduces the cost of VoIP support. As a result, more gateway vendors are including VoIP in their newest products. For example, 36% of cable modems shipped in 1Q06 included voice support, up from 21% in 1Q05. Similarly, Infonetics reported 42% quarter-over-quarter growth for VoIP-enabled DSL modems in 4Q05. Gateway processors fill an important market need. The capability of these chips will evolve rapidly to meet the changing requirements of broadband and home networks.
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