Processor Conference 2013
Conference Proceedings Available Now
Held on October 16 - 17, 2013

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Agenda for Day One: October 16, 2013
View Day Two

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9:00am-9:45amKeynote

Keynote: Overview of the market and technology trends affecting processors for networking
Linley Gwennap, Principal Analyst, The Linley Group

This presentation gives an overview of market, technology, system-design, and silicon trends for processors for networking and communications infrastructure. The presentation will include relevant market data for 2012 and forecasts for 2013 and beyond. It will also present an independent view of the leading processors and discuss the factors that will determine which processors will succeed in these markets.

9:45am-12:00pmSession 1: Trends in Multicore-Processor Design

Multicore processors sit at the center of any networking or communications system. This session, moderated by principal analyst Linley Gwennap, explores how companies designing multicore technologies adapt to the newest market requirements. It includes the first technical disclosure of three new processors.

Delivering >2X Performance Gain Per Core in Single-Generation Upgrade
David Hass, CTO, Processors and Wireless Infrastructure, Broadcom

Next-generation infrastructure, data center and enterprise networks are demanding a significant boost in performance while maintaining the same stringent power profile. This presentation will introduce a new CPU microarchitecture that will deliver over 2x performance gain for each processor core in a single-generation migration, while minimizing power consumption. These CPU innovations, coupled with best-in-class communications and networking system-on-a-chip technologies, will improve scalability and performance/watt for next-generation system solutions.

Dual Mode Small Cells for HetNets
Raj Singh, GM Wireless Broadband Group, Cavium

Small-cell technology has evolved significantly from the relatively simple 3G femtocell for residential use. New dual-mode (HSPA+/LTE) small cells offer sophisticated features previously found only on pico/macrocells. Users can seamlessly transfer from macro to small cell and back again. Operators are specifying small cells based on single-chip SoCs for removing dead spots and significantly increasing capacity by offloading the macrocell network. This presentation will show how a combination of high-performance, low-power multicore processors with dynamically configurable L1 physical layers enables rapid development of dual-mode small cells.

Break Sponsored by Freescale

The High-End Embedded Processor Power-Performance Paradox
Yankin Tanurhan, VP of R&D, Synopsys

Designers of performance-intensive, high-end embedded applications face growing performance requirements with increasingly stringent power budgets. Available processors that offer the needed performance require more power than the available budget, forcing engineers to make tradeoffs and deliver products that fall short of their goals. This presentation will disclose a new ARC processor that solves this paradox by delivering high performance while cutting power consumption.

Lending an ARM to the Networking World
David Kramer, Director of Freescale Discovery Labs, Freescale

Next-generation networks are moving to open hardware and software systems that can accommodate the fluid nature of a virtualized compute and storage cloud. These networks need a portfolio of balanced processors containing common platform coherent interconnect, I/O connectivity, virtualized and optimized networking interfaces, the latest high-speed memory interfaces, and a broad software ecosystem. This presentation debuts Freescale's first family of products based on Layerscape architecture, the QorIQ LS1 family, which incorporate dual ARM CPUs and are designed to meet the demands of next-generation virtualized networks.

Q&A and panel discussion featuring the above speakers.

12:00pm-1:15pmLunch - Sponsored by Cavium
  Track A - Communications System Design Track B - Communications SoC Design
1:15pm-2:45pmSession 2: High-Performance Memories for Networking

Innovative memory designs are needed to process packets at high data rates. This session, moderated by The Linley Group senior analyst Jag Bolaria, examines directions in memories targeting networking applications.

Solving the Performance and Power Challenges of Next Generation 400G Systems
Jay Walstrum, Senior System Architect, Micron

For network system development beyond 100Gbps, efficiency and performance gains are becoming increasingly small and hard to achieve. Higher-performance memory solutions are needed for a variety of applications including control-plane processing and data packet buffering. This presentation will profile how Micron's Hybrid Memory Cube addresses the requirements of next-generation network communication systems, which include a 4x increase in bandwidth, flexible and intelligent memory subsystems, and a limited power envelope.

Feature-Rich 1Tbps Packet Processing Through Intelligent Offload and Storage
Michael J Miller, VP of Technology Innovation and System Applications, MoSys

System power and package interconnect to off-chip storage can limit the number of features achievable using tomorrow's network packet processors. This presentation will explain how the MoSys MSR820 Bandwidth Engine chip can increase storage performance by more than 4x through intelligent offload of counters, traffic-management leaky buckets, semaphores and transactional memory operations for link-list management. The talk will also explore storage trends such as intelligent offload of macro functions at terabit speeds.

Algorithmic Search Processor is the Future
Bing Xiong, CEO, XeL Technology

Search engines have been an important part of packet processing and with the proliferation of network data rates, and trends such as SDN/OpenFlow, the industry is in need of innovative search solutions. This presentation will reveal a different search solution that uses XeL's proprietary algorithms to deliver high search performance on large databases, at lower power and lower system cost than current solutions.

Q&A and panel discussion featuring the above speakers.

Session 4: High-Speed Interconnect for Communications SoCs

Connecting all the cores in a networking processor requires a flexible fabric capable of handing high-speed data flows. This session, moderated by The Linley Group senior analyst Kevin Krewell, looks at licensable IP for internal interconnect.

Beyond the SoC - Bringing System Awareness to the Software Level
Monica Tang, Senior Solutions Architect, ArterisIP

A Network-on-Chip (NoC) interconnect fabric is particularly suited for systems-on-chip with heterogeneous processing cores, due to its inherent flexibility, reduced power and die area, and more efficient design. Information from within the fabric can help processing cores better optimize system-wide performance and power consumption. This presentation will explain how information from NoC packet probes and transaction probes within the SoC fabric can be used by operating system and middleware schedulers to more efficiently utilize on-chip resources, allowing on-chip IPs to waste fewer cycles, run at lower clock rates, finish their tasks sooner, and spend more time powered down.

Coherent Interconnect Technology Supports Exponential Data-Flow Growth

The exponential growth in data consumption over multiple radio technologies requires a range of new designs for wireless infrastructure. Utilizing C-programmable multicore processors with offload acceleration, next-generation infrastructure equipment requires higher CPU-core counts and high-performance cache-coherent interconnect between cores and accelerators to enable effective scaling. This presentation details future ARM backplane and internal fabric technology to enable system designers to efficiently handle 64-bit data flows and scale beyond today's quad-core processors.

A Cache-Coherent, Scalable, Network-on-Chip
Joe Rowlands, Chief Architect, NetSpeed Systems

The growing number of IP blocks in a SoC, increasing design complexity and the paradigm shift towards hardware-driven coherency have created a need for scalable, coherent interconnect solutions. This presentation explains how NetSpeed Gemini uses a number of proven algorithms to optimize interconnects, providing a scalable, high performance, correct-by-construction network-on-chip solution. Its coherency architecture is based on an innovative directory that scales the number of coherency modules depending on high-level SoC specifications while dramatically reducing area and power.

Q&A and panel discussion featuring the above speakers.

2:45pm-3:05pmBreak - Sponsored by Freescale
3:05pm-4:40pmSession 3: Software / Hardware Codesign in Communications Systems

To optimize today's complex communications systems, software designers and hardware designers must work hand in hand. This session, moderated by The Linley Group senior analyst Tom Halfhill, discusses implementation approaches for networking software and how they affect the design of the underlying processors.

Fast Exploration of Algorithm Parallelization Options with Guaranteed Correctness
Steve Cox, VP Business Development, Target Compiler

Multicore architectures are now status quo in most ASSPs. Software developers need to parallelize their code to take advantage of the architecture, but there are too many options and no clear answers. Typical approaches focus on only a few options, and once the stakes are set, the solution can only be nudged toward better performance, leaving altogether better solutions unexplored. MP Designer presents an alternative, enabling faster exploration of multiple options to bring better solutions to the surface.

Foundation Technology for the Transition to Virtualized Networks
Rob Oshana, Director R&D, Digital Networking, Freescale

Virtualization is ushering networking into an era of rapid change. SDN and NFV are changing how networks are implemented. Open-source technologies are reducing the time between innovation and implementation. A common theme is the heightened role of software and, therefore, processors. OEMs face a dizzying array of application programming interfaces, open-source communities, and standard Linux distribution technologies. Freescale coalesces these elements into building blocks for OEMs. This presentation addresses the software technologies, standards, and solutions for next-generation virtualized networks.

Comparative Analysis of Processors in SDN and NFV Environments
Rob Truesdell, Product Manager, Software, Netronome

Software-defined networking and network-function virtualization solve many challenges, but one size does not fit all for data-plane processing. This presentation describes the practical use of SDNs, ranging from OpenFlow and security middleboxes. The talk will also present a comparative analysis of processors as they relate to these use-cases.

Q&A and panel discussion featuring the above speakers.

Session 5: Licensable Cores for Wireless Baseband

Rapidly evolving wireless protocols require high signal-processing performance with a flexible programming model. This session, moderated by The Linley Group senior analyst Mike Demler, discusses how licensable IP cores can meet these needs while reducing your design time.

The Tenth Generation Xtensa Customizable Processor

The next generation of Tensilica Xtensa customizable processors, being introduced at this conference, are optimized, tightly coupled DSP offload processors with a higher performance memory subsystem, enhanced debug support and significant power savings. Designed for high-speed innovative dataflow, this new generation has the flexibility to be ideal for data-intensive mobile, enterprise and carrier applications.

A Scalable Multicore Architecture for Next-Generation Wireless Applications
Eyal Bergman, VP of Product Marketing, CEVA

To support rapidly growing data rates, wireless SoCs are adopting advanced multicore architectures that mix CPUs, DSPs and hardware accelerators. This presentation highlights the main challenges in designing a multicore SoC for wireless-infrastructure applications, including hardware-software partitioning, data traffic management, dynamic task scheduling, data sharing and coherency, multi-mode support and more. It also explores the innovative features of the CEVA-XC flagship DSP platform that supports multicore SoCs using a scalable cluster-based system architecture.

Cloud Radio Access Networks - The Last Bastion of Network Function Virtualization
Gilad Garon, CEO, ASOCS

The true revolution of C-RAN is the virtualization of base-station resources as well as hardware/software decoupling. Virtualization only makes sense once the L1/PHY turns into a software play. Intel/AMD x86 as well as ARM-based servers will displace DSP & SoC products. Alas, general-purpose processors can't effectively run most of the modem tasks, so domain-specific hardware acceleration is still needed. This presentation discusses the ASOCS Modem Processing Unit as a coprocessor solution for C-RAN, specifically addressing a software framework called Modem Processing Language.

Q&A and panel discussion featuring the above speakers.

4:40pm-6:00pmReception and Exhibits - sponsored by Applied Micro Circuits

 

Premier Sponsor

Cavium Networks

AppliedMicro

Platinum Sponsor

Freescale

Gold Sponsor

EZchip

Broadcom

Xilinx

LSI

Micron

Tilera

ASOCS

Target

Andes Technologies

NetSpeed Systems

Industry Sponsor

EEMBC

HyperTransport Consortium

Power.org

Ethernet Alliance