Linley Processor Conference 2016
Focusing on embedded processors for communications, automotive, and IoT
Held On September 27 - 28, 2016
Hyatt Regency, Santa Clara, CA

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Agenda for Day One: September 27, 2016
View Day Two

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9:00am-9:45amKeynote

Specialization Spurs Processor Innovation
Linley Gwennap, President, The Linley Group

As Moore's Law comes to an economic halt, processor designers are scrambling to find new ways to improve performance and power efficiency. Large general-purpose CPUs are still good for some problems, but we are seeing greater use of custom architectures that are optimized for specific applications. The most recent examples are new architectures for deep learning and vision processing. This keynote presentation discusses the latest processor design trends along with our updated processor market size and forecast data.

9:45am-10:45amSession 1: IoT Edge

Intelligent edge devices create a buffer between numerous IoT clients and the rest of the Internet. To minimize the cost and power consumption of client devices, these IoT edge systems may offload complex protocols such as security. This session, moderated by The Linley Group senior analyst Loyd Case, will discuss potential threats to IoT security and provide hardware and software solutions to defend against these threats.

Protecting IoT Edge Devices from Malicious Physical and Software Attacks
Fergus Casey, Senior R&D Manager, ARC Processors, Synopsys

This presentation will discuss threats to IoT security and hardware-rooted processor security solutions that defend against these threats. It will address logical, software, hardware and physical attacks, giving special attention to countermeasures for side-channel analysis (SCA) attacks, non-invasive physical attacks that reconstruct secret cryptography keys from information leaked from an SoC's power consumption or electromagnetic radiation. Obtaining these secret keys through SCA attacks is surprisingly easy; as a result, SCA countermeasures have become fundamental to evolving IoT standards.

Securing Edge Devices in Emerging Intelligent Networks
Iisko Lappalainen, Senior Manager, Technical Pre-Sales and Solutions, Cavium

With the proliferation of IoT clients and NFV/SDN solutions, intelligent edge devices are always connected and offer new attack surfaces. Securing them is critical to preserve privacy and avoid severe financial and reputation damage. This talk will discuss building a root of trust and security in embedded platforms using ARM hardware with Linux and other open-source software. We will review hardware authentication and examine the solutions for managing run-time system integrity and domain isolation to deploy applications in secure environments. We will cover technologies such as CPU affinity, LXC and Docker containers, the KVM hypervisor, ARM's TrustZone, Security-Enhanced Linux (SELinux), and the Linux Integrity Measurement Architecture (IMA).

There will be Q&A and a panel discussion featuring above speakers.

10:45am-11:05amBreak - Sponsored by NXP
11:05am-12:30pmSession 2: IoT Client

As every thing becomes connected to the Internet, the IoT spans a broad range of client devices from connected smoke detectors to drones. All of these devices face common challenges of reducing cost and power while still delivering the capabilities that consumers want. This session, moderated by The Linley Group senior analyst Loyd Case, will discuss new technologies that support the design of IoT processors and systems.

New IP Solutions for IoT SoC Designs
Frankwell Lin, President, Andes Technology

Even as the trend for IoT continues, the scope of IoT devices is becoming more consolidated. Cloud-computing nodes and machine-to-machine links will provide explosive industry growth. This presentation will introduce various grades of new embedded microprocessor cores, peripherals, and a bus fabric to support IoT SoC designs. Features, performance, benchmarks of new Andes IP cores will be presented and promotion program will be highlighted.

Resolving the eXecute-in-Place (XiP) Challenge for IoT and Wearables
Gideon Intrater, CTO, Adesto Technologies

IoT and wearable devices challenge our low-power design techniques. While last decade's mobile phones were at the forefront of low-power design, new IoT and wearable devices require more aggressive design techniques. Consumers want high functionality, but won't settle for limited battery life. The presentation will discuss a new approach for XiP design, how it impacts the CPU's memory hierarchy and the non-volatile memory (NVM) device, compare it to traditional solutions and show how it contributes to an improved system design.

IoT with Deep Learning and Machine Learning Capabilities
Marc Naddell, VP, MediaTek Labs, MediaTek

IoT applications such as robots, drones, point-of-sale equipment, and virtual-reality headsets present challenging requirements. The processor must deliver high performance, support capabilities such as machine learning and vision, and yet be easy to design-in and program using an open-source environment. This presentation will discuss how the MediaTek x20 Hardware Development Kit, based on smartphone technology, gives developers a fast start when designing an advanced IoT project.

There will be Q&A and a panel discussion featuring above speakers.

12:30pm-1:50pmLunch Sponsored - by MediaTek
  Track A Track B
1:50pm-3:30pmSession 3: Scaling to 100Gbps and Beyond

SDN and NFV centralize and increase performance requirements for data processing, which in turn place greater demands on memories to scale up with this performance and ensure a secure end-to-end connection. This session, moderated by The Linley Group principal analyst Jag Bolaria, shows how to remove networking bottlenecks and scale up performance in a secure environment.

Developing Flexible, Scalable, Programmable Network Elements With Customizable Search Engines
Michael J Miller, VP of Technology Innovation and System Applications, MoSys

The emergence of SDN, NFV, the P4 language, and 100GbE are driving a requirement for flexible performance using programmable, algorithm-based search solutions in switches, servers, routers, security appliances and white boxes. MoSys has developed its Programmable Search Engine with optimized search processors and integrated high-performance memory to support aggregate rates ranging from 100Gbps to 1Tbps. This presentation will describe its multi-core microarchitecture and instruction set, which has been engineered to achieve up to 1 billion searches per second.

Layer 2 MACsec Security Solutions for 400GE, FlexEthernet and Beyond
Bart Stevens, VP Silicon IP and Secure Protocols Business Line, INSIDE Secure

With the ever-increasing bandwidth requirements and network speeds, protecting the data traversed through networks in an efficient way becomes an absolute must. In wired networks, the MACsec protocol allows efficient scaling to support extreme port bandwidths such as 400GE. Meanwhile, the OIF is advocating FlexEthernet instead of link aggregation to fill the gaps and supporting multiple interfaces. This presentation will explore the dedicated crypto and security-protocol accelerators for enabling security in high-speed Ethernet and FlexEthernet solutions while controlling area and power consumption.

GDDR Bandwidth Breakthrough Attracts Networking Applications
Jay Walstrum, Senior System Architect, Micron

By achieving greater than 12Gbps throughput, graphics memories are becoming a compelling option for demanding networking applications. In this talk, Micron will share successful uses of GDDR in networking designs. It will dive into the new features of GDDR designs and illustrate how those are expanding graphics performance and making cutting-edge GDDR a viable memory alternative in the networking space.

There will be Q&A and a panel discussion featuring above speakers.

Session 5: SoC Connectivity

The number of IP blocks in a processor continues to rise. Many of these blocks perform some sort of processing, including CPUs, GPUs, DSPs, and image processors (ISPs). The newest trend is to connect these heterogeneous IP cores using a cache-coherent interconnect, simplifying data sharing. This session, moderated by The Linley Group senior analyst Tom Halfhill, will discuss network-on-a-chip (NoC) and other interconnect IP for complex SoC designs.

Building More Powerful Infrastructure SoCs from Edge to Cloud
Jeff Defilippi, Senior Product Manager, ARM

Cloud computing will enable distributed intelligence across the network. Estimates indicate that these new use cases will require a 10x increase in SoC efficiency. This talk will introduce ARM's next-generation coherent backplane IP that enables SoC architects to address these challenges using heterogeneous solutions that blend compute and acceleration. Benefits include improved performance, simplified software development and ease of deployment across a range of devices from 2-Watt network access points to 100-Watt servers.

Coherency: The New Normal in SoCs
Anush Mohandass, Vice President, Marketing and Business Development, NetSpeed Systems

Today's SoCs include a mix of CPU cores, computing clusters, GPUs and other computing resources and specialized accelerators. Getting heterogeneous processors to communicate efficiently is a daunting design challenge. A popular approach is to use high-performance and power-efficient shared-memory communication and a sophisticated on-chip cache-coherent interconnect. This presentation will introduce a new technology that automates the architecture design process, supports CHI and ACE in one design, and uses advanced machine-learning algorithms to create an optimal pre-verified cache-coherent solution.

Implementing Cache-Coherent Hardware Acceleration for ADAS and Machine Learning
Matthew Mangan, Corporate Applications Engineer, Arteris

ADAS and Machine Learning Systems are unique in their use of custom acceleration hardware in heterogeneous SoCs to perform extremely complex calculations in near real time. Although these accelerators are on-chip, they often do not have caches and must communicate with the system through low-latency DRAM or by using complex messaging schemes. New technology allows existing accelerator hardware to more efficiently communicate in the system through the use of dedicated proxy caches integrated in an on-chip cache-coherent interconnect.

There will be Q&A and a panel discussion featuring above speakers.

3:30pm-3:50pmBreak - Sponsored by NXP
3:50pm-5:00pmSession 4: Virtual Network Functions

Telcos and cloud service providers are shifting away from costly specialized equipment to standard platforms capable of implement virtual network functions (VNFs). This in turn creates a richer ecosystem, reduces market-entry barriers, and fosters greater innovation. This session, moderated by The Linley Group principal analyst Jag Bolaria, will illustrate the range of VNFs possible on standard platforms.

Virtualization for Premise-Based Networking Equipment
Sam Fuller, Head of Strategy & System Solutions, Digital Networking, NXP

As more service providers look to deploy NFV throughout their networks, the impact of this approach especially with respect to virtualized customer premise equipment (vCPE) creates the need for new NFV software and hardware solutions. This presentation will discuss specific ARM multicore SoCs and software platforms designed to support vCPE applications.

NFV and SDN Solutions for IoT and 5G Intelligent Networks
Kin-Yip Liu, Sr. Director, Solutions Architecture, Cavium

NFV, SDN, and 5G enable intelligent, flexible, and efficient networks with massive connectivity, service agility, and performance scalability. Their synergy creates new services at the network edge, leading to better user experience and revenue-generating opportunities. This talk examines several new edge services, the processing requirements, a reference system architecture, and example SoCs optimized for the new intelligent edge.

There will be Q&A and a panel discussion featuring above speakers.

Session 6: Server Processors

Several vendors have recently emerged to supply server processors into cloud data centers. These vendors are challenging Intel's popular Xeon products with new processors using RISC instruction sets. This session, moderated by The Linley Group senior analyst Tom Halfhill, includes presentations on two Xeon-class products, one using the ARM architecture and one using the POWER architecture.

An Advanced RISC SoC for Cloud Computing
Kumar Sankaran, Associate VP, Software and Platform Engineering, AppliedMicro

RISC processors today are being deployed for workloads such as enterprise storage, control-plane equipment, web servers, high-performance computing, in-memory databases, and security appliances. Next-generation processors using FinFET technology will offer a quantum leap in performance and target mainstream cloud workloads such as web-caching servers, web search, data analytics, and machine learning. This presentation will describe use cases for the initial X-Gene processors and provide a preview of the next-generation X-Gene 3 product.

POWER9: A Processor for the Cognitive Era
Brian Thompto, Senior Technical Staff Member, IBM

This presentation describes features of the POWER9 family, with optomizations for one- and two-socket servers, DDR4 direct -attached memory, PCI Express Gen 4, and mulitsocket enterprise servers with robust buffered memory systems. The design includes a new one core microarchitecture featuring execution-slice technology, delivering enhanced performance with improved execution efficiency. The new design includes intelligent features for optimizing cloud workloads and improves virtualization efficiency. It features a robust set of accelerated heterogenous computing technologies, enabling innovative solutions in the OpenPOWER ecosystem.

There will be Q&A and a panel discussion featuring above speakers.

5:00pm-6:30pmReception and Exhibits - Sponsored by Synopsys

 

Platinum Sponsor

Cavium Networks

Gold Sponsor

CEVA

NetSpeed Systems

Micron

Andes Technologies

AppliedMicro

Industry Sponsor

EEMBC

Media Sponsor