Linley Processor Conference 2016
Focusing on embedded processors for communications, automotive, and IoT
Held On September 27 - 28, 2016
Hyatt Regency, Santa Clara, CA

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Agenda for Day Two: September 28, 2016
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9:00am-9:45amKeynote

How Virtualization is Changing Networking
Bruce Davie, CTO, Networking and Principal Engineer, Networking and Security BU, VMware

The concept of network virtualization is not new, but has risen to prominence in recent years as a result of both new technologies (e.g., software-defined networking (SDN)) and new challenges (e.g. security in data centers and "the cloud"). This talk will trace the rise of network virtualization from research project to widely deployed technology. We'll also look at its likely impact on the future of networking, including the increased need for programmable network hardware. The combination of more capable hardware and new approaches to networking software will enable us to tackle a range of long-standing networking challenges.

9:45am-10:45amSession 7: Cloud Acceleration

Cloud data centers perform a variety of different workloads. Some of these workloads perform well on general-purpose servers, but others can be offloaded to more efficient special-purpose processors. This session, moderated by The Linley Group principal analyst Linley Gwennap, will introduce a new architecture optimized for deep learning as well as a new processor that offloads high-speed security tasks.

A Novel Dataflow Processing Technology for Deep Learning
Chris Nicol, Chief Technology Officer, Wave Computing

Dataflow Processing Units (DPUs) provide native support of deep-learning frameworks like TensorFlow and CNTK. DPUs exploit data and model parallelisms in deep learning by leveraging tens of thousands of processing nodes, massive amounts of local and external memory bandwidth with real-time reprogrammability, delivering unparalleled performance. Wave is developing a family of Deep Learning Computers based on DPUs to deliver faster training and inference for cloud, data-center and on-premise environments. This presentation will introduce the microarchitecture of the company's first DPU.

Democratizing Security: Painless Encryption for Every Server Port
Bob Doud, Sr. Director of Marketing, Mellanox

Data center operators require security technologies such as IPsec or TLS encryption/authentication between their servers, gateways and client nodes to protect data-in-transit. However, these encryption workloads consume revenue generating server processor cycles, inhibiting the broad deployment of over-the-wire security. Mellanox will debut its Innova Secure network adapter solution that offloads and accelerates security protocols and advanced network functions, enabling the ubiquitous use of encryption across the data center with the highest network throughput and superior server utilization.

There will be Q&A and a panel discussion featuring above speakers.

10:45am-11:05amBreak - Sponsored by NXP
11:05am-12:00pmSession 8: Open Instruction Sets

Most processors today use one of a handful of popular instruction sets. These instruction sets have one thing in common: all are owned and administered by a single company. ISA licenses are often expensive and can be restrictive. This session, moderated by The Linley Group principal analyst Linley Gwennap, will discuss the ramifications of a new open-source instruction set that is freely available for anyone to use.

RISC-V: Instruction Sets Want To Be Free
Krste Asanović, Professor, EECS Department, University of California, Berkeley and Chairman, RISC-V

The most important interface in a computer system is the instruction set architecture (ISA). A free ISA is necessary to future hardware innovation. There is no good technical reason not to have free, open ISAs, just as we have free, open networking standards and free, open operating systems. This presentation will cover the technical features of the RISC-V ISA design, three different industry-competitive open-source cores developed at UC Berkeley, and the development of the RISC-V ecosystem, including the RISC-V Foundation.

Free Instruction Sets: It Costs You Somewhere
Markus Levy, President, EEMBC

Why do proprietary instruction sets still dominate the market? The answer: economics and time to market. The ISA isn't that important anymore; instead, the SoC design is the primary driver. For example, this is evidenced as EEMBC benchmarks evolve from a focus on the processor core to system-level benchmarks. For semiconductor companies, margin and volume are key. Licensing a core adds little to the end cost of the device but can save a lot of NRE.

There will be Q&A and a panel discussion featuring above speakers.

12:00pm-1:20pmLunch Sponsored - by MediaTek
1:20pm-2:15pmSpecial Session: Enabling Self-Driving Cars to See

To enable self-driving cars to safely navigate their environments, they must be capable of "seeing" at least as well, if not better than humans. They must be able to detect and recognize objects, people, roadways, traffic signs, and other vehicles, and place them accurately to synthesize a 3D view. Their vision will come from an array of sensors, including cameras, lidars, radars, and ultrsonic detectors. This special session, moderated by The Linley Group senior analyst Mike Demler, will focus on the challenges of enabling self-driving cars to see.

Autonomous Cars Approaching Fast
Mike Demler, Senior Analyst, The Linley Group

Although products such as Tesla's Autopilot and Volvo's Pilot Assist require human supervision, vehicles that can self-drive under at least some circumstances will arrive within two years, and Ford has promised to deliver a self-driving car without a steering wheel by 2021. These vehicles require far more processing power and sensor content than today's cars. Mike Demler, the lead automotive analyst for The Linley Group, will provide a brief overview of the processors and sensors required for autonomous driving and a new forecast for self-driving technology.

Advanced Sensors for Autonomous Vehicles
Louay Eldada, CEO and co-Founder, Quanergy Systems, Inc.

To obtain a complete picture of their environment, self-driving cars require an array of sensors. Radar and lidar can supplement cameras by providing a 3D view with accurate range information, but these systems can be quite expensive. This presentation will address these trends while describing a new solid-state lidar system that achieves automotive reliability and cost targets while improving range, resolution, accuracy, and speed of objects detection.

The session will include a fireside chat with the two speakers, followed by audience Q&A.

2:15pm-3:00pmSession 9: Automotive and Vision

Advanced driver assistance systems (ADAS) are evolving from delivering hazard warnings, to active collision-avoidance, to fully autonomous driving. Specialized computer-vision IP cores coupled with deep-learning processors will provide the eyes and brains for future smart cars. This session, moderated by Mike Demler, senior analyst at The Linley Group, discusses new IP and SoC architectures for ADAS and other automotive applications.

Processing for Intelligent Transportation Systems (ITS) infrastructure
Geoff Waters, Senior Principal Engineer – Security, Digital Networking, NXP

Intelligent Transportation Systems (ITS), including Roadside Units (RSUs) and smart intersections, will play a critical role in helping connected and automated vehicles meet their potential for increased safety, decreased commute times, and energy savings. This presentation examines the sensing, processing, communications, and security requirements for smart intersections, and how these requirements may be best met.

A Neural-Network Oriented Vision DSP with Customized Hardware and Software Framework
Liran Bar, Director of Product Marketing, CEVA

As artificial intelligence continues its relentless evolution, one of the major challenges is how to successfully integrate it into the small, low-power devices we use in our everyday lives. The deep neural networks underlying AI require high-performance yet power-efficient embedded platforms. This presentation will introduce the latest CEVA vision processor and demonstrate how its neural-network software framework and unique "push button" network converter converts pre-trained networks to real-time optimized networks for embedded devices, significantly reducing time-to-market.

3:00pm-3:20pmBreak - Sponsored by NXP
3:20pm-4:40pmSession 9: Automotive and Vision (cont)

High-Performance Vision Processors for HD Resolutions at Embedded Power Levels
Mike Thompson, Sr. Product Marketing Manager, ARC Processors, Synopsys

The availability of high-performance vision processors makes it possible to integrate vision capabilities into embedded SoCs, giving them the ability to see and interpret their surroundings. The challenge is to do this at power-consumption levels compatible with embedded systems. This requires a specialized approach to processor design and flexibility in the implementation of the processor and tools while addressing the latest embedded vision programming standards.

As Embedded Floating Point Becomes Ubiquitous, What Are Your Options?
Dror Maydan, Senior Group Director, Tensilica Software Group, Cadence

Today's vehicles and handsets need to be more interactive, safer, and easier to use while processing real-world data from a variety of sensors. Floating-point algorithms are increasingly being used for higher accuracy and reduced development cycles. SoCs processing this data need to efficiently handle both fixed- and floating-point operations. This presentation will demonstrate how designers can quickly implement programmable, differentiated, and power-efficient real-time signal processing using Cadence Tensilica's extensive portfolio of floating-point digital signal.

There will be Q&A and a panel discussion featuring above speakers.

4:40pmConference Ends

 

Platinum Sponsor

Cavium Networks

Gold Sponsor

CEVA

NetSpeed Systems

Arteris

RISC-V

ARM

Micron

Andes Technologies

AppliedMicro

Industry Sponsor

EEMBC

Media Sponsor