Linley Tech High-Speed Interconnect Seminar

Held November 3, 2010

» Events  |  Proceedings

If you are using or evaluating interconnect technologies for your designs, then you won't want to miss our Linley Tech seminar on High-Speed Interconnects coming to San Jose on November 3.

We brought together industry leaders to discuss the latest products and technologies for system-level interconnects and recent developments at the physical layer for various protocols.

With speeds ranging from 3Gbps to 40Gbps and 100Gbps, these interconnects are used at the board level, over the backplane, chip-to-chip, and between systems. This seminar delivers a wealth of information including interconnect technologies, developing standards, and technology trends.

Our outstanding lineup of presenters, included:
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Michael Miller, Vice President of Technology Innovation and System Applications, MoSys
Bandwidth Density Challenge Beyond 100Gbps
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Vijay Meduri, Vice President of Engineering, PLX Technology
PCI Express as a Clustering and Remote-I/O Interconnect
> Dariush Dabiri, Director of Systems Engineering, AppliedMicro
Electromagnetic Interference Cancellation for 10GBASE-T Receiver: New Challenges for Coexistence Between Wireless and Wireline Communication Systems
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Nafea Bshara, CTO, Enterprise Business Unit, Marvell
40GbE Ethernet for Low-latency HPC Applications
> Toby Foster, Product Marketing Manager, Network Systems Division, Freescale
Meeting the Challenges of High Speed Connectivity in Embedded Applications
> Katharine Schmidtke, Strategic Technology Initiatives, Finisar
Technology Advancements in High-Bandwidth Optical Interconnects
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Trevor Hiatt, Senior Product Manager, IDT
Technical Comparison of Ethernet and RapidIO in Intra- and Inter-chassis Usage
> Panch Chandrasekaran, Sr. Marketing Manager, and
Anthony Torza, Sr. Technical Marketing Manager, Xilinx

Building Optically Compliant High Performance Serial Links