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October 24, 2016

  • Apple W1 Processor Powers Airpods (MCR)
    To develop its new wireless Airpod earphones for the iPhone 7, Apple designed the W1 wireless processor, which overcomes limitations in the Bluetooth specification for advanced audio distribution.
  • Editorial: Intel Unarmed in M&A Battle (MPR)
    Intel’s ARM-avoidance policy constrains its acquisition strategy, as recent purchases of Movidius, Nervana, and Soft Machines demonstrate. Qualcomm’s proposed NXP deal provides a stark contrast.
  • Qualcomm Previews 5GTF Modem (MCR)
    In 2018, Qualcomm will deploy a 5G-class modem called the X50. Instead of the full 5G standard under development by 3GPP, this chip will implement the simpler 5GTF standard.
  • Adapteva’s Million-Dollar Epiphany (MPR)
    Adapteva’s 1,024-core Epiphany-V should deliver 2Tflop/s of double-precision performance at 30W. More remarkably, the 16nm FinFET design took less than $1 million to tape out.

October 17, 2016

  • Apple A10 Bruises Other CPUs (MPR/MCR)
    The iPhone 7 uses two new custom ARM CPU designs to deliver better performance than any other smartphone, although the big Hurricane CPU consumes plenty of die area.
  • AppliedMicro Leaps to 100Gbps PAM4 (NWR)
    AppliedMicro recently demonstrated in conjunction with Macom and BrPhotonics a 100Gbps PAM4 link over single-mode fiber. It expects single-wavelength 100Gbps links to bypass 50Gbps-per-lambda alternatives.
  • Nvidia Tunes Pascal for Learning (MPR)
    The Tesla P4 and P40, due to enter production in 4Q16, are second-generation machine-learning accelerators that use the new Pascal architecture for up to 10x performance gains.

October 10, 2016

  • Adesto Executes in Place (MPR)
    The new EcoXIP memory combines standard NOR flash with a custom high-speed interface designed specifically for streaming instructions in MCU-based IoT applications.
  • Flex Logix Adds 40nm for MCUs (MPR/NWR)
    Flex Logix, a startup specializing in FPGA intellectual property, has designed cores for a mature 40nm TSMC process (40ULP), even as it simultaneously characterizes its FinFET cores.
  • Helio X30 Targets 10 Cores at 10nm (MCR)
    MediaTek’s next-generation flagship processor will be one of the first smartphone chips built in TSMC’s 10nm technology. It will likely appear in phones around mid-2017.
  • Ceva XM6 Accelerates Neural Nets (MPR)
    The new XM6 DSP core enables deep learning in embedded computer-vision processors, targeting self-driving cars, augmented and virtual reality, surveillance cameras, drones, and robotics.

October 3, 2016

  • Wave Accelerates Deep Learning (MPR)
    Startup Wave Computing has created an innovative dataflow architecture, implemented in a processor with 16,384 cores, that offers a 10x speedup for training neural networks.
  • Andes E830 Extends Processor IP (MPR)
    The new Andes E830 is a user-extensible CPU core with an updated and more compact instruction set. The company has also solidified its interconnect-design portfolio by adding the AE300.
  • Cortex-R52: Safer Real-Time Control (MPR)
    ARM’s new core supersedes the Cortex-R5 by adding virtualization, greater throughput, better lockstepping, and optional Neon extensions while increasing real-time deterministic performance.
  • GlobalFoundries Offers 7nm Roadmap (MPR)
    For its FinFET technology, GlobalFoundries is skipping 10nm and moving to a 7nm process targeting for 2018 production. Its new 12nm FD-SOI process offers an alternative path forward.

September 26, 2016

  • Samsung Unveils Custom M1 Core (MPR/MCR)
    Taking a page from rival Qualcomm’s book, Samsung designed a custom ARM CPU for the Exynos 8890, its first smartphone processor to forgo using a standard Cortex core.
  • Phytium Samples 64-Core ARMv8 (MPR)
    The Chinese startup is sampling its FT-2000/64—the world’s biggest ARM-compatible server processorand disclosed 4- and 16-core ARM chips that are already in production.
  • Broadcom Redefines Gearbox Ports (NWR)
    Broadcom is in early production with three PHYs that implement retiming beyond the original 4:10/10:4 gearbox function and provide extensions from the emerging Multi-Link Gearbox 2.0 standard.
  • Editorial: ADAS Opportunities Expand (MPR)
    Despite the attention on self-driving cars, automotive-processor vendors will find that active-safety systems present a bigger and fast-growing opportunity over the next several years.
  • Low-End Exynos Moves to 14nm (MCR)
    Taking sales from Qualcomm, Samsung has built a budget smartphone processor using its own 14nm FinFET process, integrating LTE, Wi-Fi, Bluetooth, and GPS functions.
  • Synopsys Debuts Secure ARC Cores (MPR)
    Two new DesignWare cores improve security in IoT devices and embedded systems using features such as secure containers and countermeasures against side-channel attacks.

September 19, 2016

  • Oracle Sparc Accelerates Big Data (MPR)
    Oracle’s recent Sparc processors integrate hardware acceleration for database software, big-data analytics, and security. They also enable compression of in-memory databases.
  • Sentons Channels Ultrasound Touch (MCR)
    Using its Zero Deflection Force products, startup Sentons has delivered ultrasonic touch capability, which eases implantation of force touch as well as novel touch applications.
  • Editorial: Common PHY Standards Needed (NWR)
    Fibre Channel and InfiniBand have both seen a longer lifespan in the data center than skeptics anticipated, but the justification for independent physical-layer standards to support these protocols is waning quickly.

September 12, 2016

  • Vesper Mic Drops Under Water (MCR)
    Using piezoelectric materials in a MEMS microphone, startup Vesper offers immunity from dust and liquids and better power consumption than traditional capacitive MEMS mics.
  • Intel Unveils Silicon-Photonics MSAs (NWR)
    Intel has finally announced two 100Gbps silicon-photonics offerings for the data center: a parallel single-mode PSM4 module that’s in production and a CWDM4 module that’s in early sampling. 

September 5, 2016

  • IBM Power9 Scales Up and Out (MPR)
    IBM’s next-generation Power9 server processors are branching out into four initial designs. In addition to having 12 or 24 cores, the scale-up versions will use external memory buffers, and the scale-out versions will integrate DRAM controllers.
  • NVMe Seeks Best Fabric Fit (NWR)
    Several vendors have recently demonstrated applications based on the NVM Express over Fabrics standard. Adherence to standards, however, doesn’t always result in compatibility.

August 29, 2016

  • AMD Finds Zen in Microarchitecture (MPR)
    Providing a fresh start for AMD’s computing ambitions, Zen offers 40% better performance than the prior generation and is the company’s first CPU in a FinFET node. 
  • MaxLinear Completes Backhaul Design (NWR)
    MaxLinear is sampling its first single-chip microwave-backhaul radio. Modjeska (MxL110X) works with a modem chip that came from the company’s recent acquisition of Broadcom’s wireless-backhaul business. 

August 22, 2016

  • Akoustis Challenges Broadcom FBAR (MCR)
    A startup company is using a new single-crystal manufacturing process to build RF filters for the LTE high band. It claims these filters will surpass the industry leader’s performance.
  • Comms Semis Look Beyond M&A (NWR)
    Consolidation has left a stronger field of IC vendors in networking and communications. The leaders will benefit from an improving market in 2016.
  • EEMBC Upgrades Auto Benchmarks (MPR)
    The leading provider of embedded-processor benchmarks has added multithreading, larger data sets, and other features to its popular AutoBench suite for automotive and industrial processors.

August 15, 2016

  • Chelsio’s Terminator Takes on 100GbE (NWR)
    Chelsio Communications’ new T6 controller chip handles new 25/50/100G Ethernet speeds while also adding encryption-offload hardware. In storage targets, it faces QLogic’s “Big Bear,” which will soon be a Cavium offering.
  • Snapdragon 820 Adds 1 (MCR)
    Qualcomm’s new Snapdragon 821 processor, debuting in the Asus ZenFone 3 Deluxe, offers a modest speed boost but still delivers the best performance of any mobile device.

August 8, 2016

  • U.S. Government Acts on 5G (NWR/MCR)
    The FCC has allocated 11GHz of millimeter-wave spectrum for 5G in the U.S., and Verizon has defined its own pre-5G radio with plans for broadband deployment next year.

August 1, 2016

  • SiFive Offers RISC-V Platforms (MPR)
    A startup founded by the creators of the RISC-V instruction set aims to reduce the cost of ASIC development by designing and selling custom chips based on open-source CPU cores.
  • Ceva X2 Controls Multiple PHYs (MPR/MCR)
    Ceva’s new X2 DSP performs physical-layer (PHY) control in complex wireless modems such as LTE-Advanced, which requires control of multiple communications channels.
  • RapidIO’s 25xN Follows Serdes Trend (NWR)
    The release of the 100Gbps RapidIO 25xN specification represents a shift toward broader use of 25Gbps lanes over short distances, matching that speed’s popularity in networking.

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