Current MPR Articles
October 24, 2016
Editorial: Intel Unarmed in M&A Battle (MPR)
Intel’s ARM-avoidance policy constrains its acquisition strategy, as recent purchases of Movidius, Nervana, and Soft Machines demonstrate. Qualcomm’s proposed NXP deal provides a stark contrast.
Adapteva’s Million-Dollar Epiphany (MPR)
Adapteva’s 1,024-core Epiphany-V should deliver 2Tflop/s of double-precision performance at 30W. More remarkably, the 16nm FinFET design took less than $1 million to tape out.
October 17, 2016
Apple A10 Bruises Other CPUs (MPR/MCR)
The iPhone 7 uses two new custom ARM CPU designs to deliver better performance than any other smartphone, although the big Hurricane CPU consumes plenty of die area.
Cadence LX7 Enables New DSP Cores (MPR)
Cadence’s Xtensa LX7 DSP core enhances the memory subsystem and system-bus interface to support new audio, communications, sensor-fusion, and vision products.
Nvidia Tunes Pascal for Learning (MPR)
The Tesla P4 and P40, due to enter production in 4Q16, are second-generation machine-learning accelerators that use the new Pascal architecture for up to 10x performance gains.
October 10, 2016
Adesto Executes in Place (MPR)
The new EcoXIP memory combines standard NOR flash with a custom high-speed interface designed specifically for streaming instructions in MCU-based IoT applications.
Flex Logix Adds 40nm for MCUs (MPR/NWR)
Flex Logix, a startup specializing in FPGA intellectual property, has designed cores for a mature 40nm TSMC process (40ULP), even as it simultaneously characterizes its FinFET cores.
New CoreLink IP Targets Servers (MPR/MCR)
ARM’s new CoreLink CNM-600 interconnect and DMC-620 DRAM controller can join up to 128 CPUs in a memory-coherent network while vastly improving performance.
Gemini 3.0 Beefs Up NoC Automation (MPR)
NetSpeed has expanded the machine-learning capability in its Gemini 3.0 tool, enabling faster and more-automatic design of the network-on-a-chip.
Ceva XM6 Accelerates Neural Nets (MPR)
The new XM6 DSP core enables deep learning in embedded computer-vision processors, targeting self-driving cars, augmented and virtual reality, surveillance cameras, drones, and robotics.
October 3, 2016
Wave Accelerates Deep Learning (MPR)
Startup Wave Computing has created an innovative dataflow architecture, implemented in a processor with 16,384 cores, that offers a 10x speedup for training neural networks.
Andes E830 Extends Processor IP (MPR)
The new Andes E830 is a user-extensible CPU core with an updated and more compact instruction set. The company has also solidified its interconnect-design portfolio by adding the AE300.
Cortex-R52: Safer Real-Time Control (MPR)
ARM’s new core supersedes the Cortex-R5 by adding virtualization, greater throughput, better lockstepping, and optional Neon extensions while increasing real-time deterministic performance.
GlobalFoundries Offers 7nm Roadmap (MPR)
For its FinFET technology, GlobalFoundries is skipping 10nm and moving to a 7nm process targeting for 2018 production. Its new 12nm FD-SOI process offers an alternative path forward.
September 26, 2016
Samsung Unveils Custom M1 Core (MPR/MCR)
Taking a page from rival Qualcomm’s book, Samsung designed a custom ARM CPU for the Exynos 8890, its first smartphone processor to forgo using a standard Cortex core.
Phytium Samples 64-Core ARMv8 (MPR)
The Chinese startup is sampling its FT-2000/64—the world’s biggest ARM-compatible server processor—and disclosed 4- and 16-core ARM chips that are already in production.
Editorial: ADAS Opportunities Expand (MPR)
Despite the attention on self-driving cars, automotive-processor vendors will find that active-safety systems present a bigger and fast-growing opportunity over the next several years.
Synopsys Debuts Secure ARC Cores (MPR)
Two new DesignWare cores improve security in IoT devices and embedded systems using features such as secure containers and countermeasures against side-channel attacks.
September 19, 2016
Oracle Sparc Accelerates Big Data (MPR)
Oracle’s recent Sparc processors integrate hardware acceleration for database software, big-data analytics, and security. They also enable compression of in-memory databases.
September 12, 2016
Intel Takes Baby Step to Kaby Lake (MPR)
The initial release of Kaby Lake is limited to high-end notebook PCs and ultra-low-power products. The new 14nm+ technology boosts the CPU speed by 4–11%.
September 5, 2016
IBM Power9 Scales Up and Out (MPR)
IBM’s next-generation Power9 server processors are branching out into four initial designs. In addition to having 12 or 24 cores, the scale-up versions will use external memory buffers, and the scale-out versions will integrate DRAM controllers.
Bluetooth 5 Boosts Range, Capacity (MPR/MCR)
Bluetooth 5 will enable greater range or lower power, add improvements to beacon mode, and set the stage for inclusion of mesh networking.
August 29, 2016
AMD Finds Zen in Microarchitecture (MPR)
Providing a fresh start for AMD’s computing ambitions, Zen offers 40% better performance than the prior generation and is the company’s first CPU in a FinFET node.
Editorial: The Post-Smartphone Market (MPR/MCR)
As smartphone growth nears zero, chip companies are turning their attention, and their engineering resources, toward emerging markets such as IoT, wearables, and autonomous cars.
August 22, 2016
EEMBC Upgrades Auto Benchmarks (MPR)
The leading provider of embedded-processor benchmarks has added multithreading, larger data sets, and other features to its popular AutoBench suite for automotive and industrial processors.
August 15, 2016
FD-SOI Offers Alternative to FinFET (MPR)
A new version of SOI technology from GlobalFoundries provides an alternative to the expensive wafers and difficult design rules of advanced FinFET processes.
August 8, 2016
VeriSilicon VIP8000 Accelerates CNNs (MPR)
A licensable core for native OpenCL vision processing that is based on Vivante GPU technology, the VIP8000 targets automotive and consumer products.
August 1, 2016
SiFive Offers RISC-V Platforms (MPR)
A startup founded by the creators of the RISC-V instruction set aims to reduce the cost of ASIC development by designing and selling custom chips based on open-source CPU cores.
Ceva X2 Controls Multiple PHYs (MPR/MCR)
Ceva’s new X2 DSP performs physical-layer (PHY) control in complex wireless modems such as LTE-Advanced, which requires control of multiple communications channels.
Fusion G3 Beefs Up Floating Point (MPR/MCR)
Cadence has developed the Fusion G3 DSP to target mobile and consumer applications, offering up to four times the performance of its Fusion F1.