Current MPR Articles
August 29, 2016
AMD Finds Zen in Microarchitecture (MPR)
Providing a fresh start for AMD’s computing ambitions, Zen offers 40% better performance than the prior generation and is the company’s first CPU in a FinFET node.
Editorial: The Post-Smartphone Market (MPR/MCR)
As smartphone growth nears zero, chip companies are turning their attention, and their engineering resources, toward emerging markets such as IoT, wearables, and autonomous cars.
August 22, 2016
EEMBC Upgrades Auto Benchmarks (MPR)
The leading provider of embedded-processor benchmarks has added multithreading, larger data sets, and other features to its popular AutoBench suite for automotive and industrial processors.
August 15, 2016
FD-SOI Offers Alternative to FinFET (MPR)
A new version of SOI technology from GlobalFoundries provides an alternative to the expensive wafers and difficult design rules of advanced FinFET processes.
August 8, 2016
VeriSilicon VIP8000 Accelerates CNNs (MPR)
A licensable core for native OpenCL vision processing that is based on Vivante GPU technology, the VIP8000 targets automotive and consumer products.
August 1, 2016
SiFive Offers RISC-V Platforms (MPR)
A startup founded by the creators of the RISC-V instruction set aims to reduce the cost of ASIC development by designing and selling custom chips based on open-source CPU cores.
Ceva X2 Controls Multiple PHYs (MPR/MCR)
Ceva’s new X2 DSP performs physical-layer (PHY) control in complex wireless modems such as LTE-Advanced, which requires control of multiple communications channels.
Fusion G3 Beefs Up Floating Point (MPR/MCR)
Cadence has developed the Fusion G3 DSP to target mobile and consumer applications, offering up to four times the performance of its Fusion F1.
July 25, 2016
Polaris Revitalizes AMD GPUs (MPR)
AMD’s 14nm Polaris architecture combines intelligent rasterization, quality of service, and novel circuit designs to nearly double performance per watt in the new Radeon RX 480.
Editorial: Intel Extends Server Control (MPR)
Initiatives such as XPoint memory and RSA give Intel more control of the server platform even to the rack level, improving its profits but hobbling its customers.
Guest Commentary: Be a HW and SW Engineer (MPR)
As the slowdown in Moore’s Law constrains hardware performance, software and hardware engineers must better understand each other’s disciplines to optimize performance.
ARM Hatching 4K Video Egil (MPR/MCR)
ARM is developing a new video core, code-named Egil, that includes enhanced HEVC (H.265) support as well as the ability to encode and decode Google’s VP9 format.
July 18, 2016
Andes N650 Targets Low-Power IoT (MPR)
Andes has developed a low-power area-efficient CPU core, the 32-bit N650, that further extends the low end of its lineup to target IoT clients with very low power requirements.
July 11, 2016
Xeon Phi 7200 Boots Up for HPC (MPR)
The initial Knights Landing products are now in production, delivering 3Tflop/s of double-precision performance with up to four times the power efficiency of Xeon E5.
In Memoriam: Michael Slater, Microprocessor Guru (MPR)
Michael Slater, founder of this newsletter as well as a friend and mentor to many of our staff, has passed away at the age of 60.
July 4, 2016
Synopsys Improves Vision With DSP (MPR)
The new DesignWare EV6x embedded-vision cores complement the ARC CPU with a 512-bit vector DSP and an optional convolutional-neural-network (CNN) accelerator.
Broadwell Accelerates the DPDK (MPR/NWR)
Intel Xeon processors are improving their networking performance through better hardware and better software—in particular, the Data Plane Development Kit (DPDK). Other vendors are following suit by adapting the DPDK to their processors.
June 27, 2016
IBM TrueNorth Tackles Deep Learning (MPR)
IBM’s neuromorphic processor tremendously improves power efficiency for certain machine-learning problems by eschewing the traditional memory model and relying on fixed-function computation.
Editorial: Learning Chips Hit the Market (MPR)
Google and IBM have already deployed custom chips optimized for deep learning, and several startups are also taking this approach, creating a new wave of microarchitecture design.
GPUs Stream Into Data-Center Xeons (MPR)
Intel’s new Xeon E3-1500v5 server processors accelerate video and graphics workloads, pairing four Skylake CPUs with a powerful GPU and a co-packaged eDRAM cache.
June 20, 2016
14nm Broadwell-EX Boosts Brickland (MPR)
The third socket-compatible processor in Intel’s Xeon E7 platform known as Brickland, Broadwell-EX boosts performance and power efficiency by up to 30% and doubles memory capacity.
High-End Mali Takes Bifrost Bridge (MPR/MCR)
ARM’s newest GPU architecture addresses the requirements of high-performance graphics and enables cache-coherent CPU/GPU operation for general-purpose-GPU (GPGPU) computing.
Marvell IAP220 Targets Smart Home (MPR)
The new IAP220 combines dual Cortex-A7 CPUs with a low-power sensor hub, making it well suited to Android-based IoT devices. It can also serve in smartwatches.
Sonics Ice-G1 Simplifies the PMU (MPR)
Sonics’ new power-management IP replaces the traditional microcontroller with a set of state machines that provide much faster and more-localized control, reducing energy consumption.
June 13, 2016
Mellanox Marries ConnectX to Tile-Mx (MPR/NWR)
The new Mellanox BlueField SoCs integrate the company’s ConnectX Ethernet adapter design with ARM Cortex-A72 CPUs and the Tilera multicore technology acquired with EZchip.
June 6, 2016
Cortex-A73 Improves Mobile Efficiency (MPR/MCR)
The new Cortex-A73 focuses on power and sustainable performance instead of benchmark scores, reducing power by 20% and die area by 25% compared with its predecessor
Cavium Beefs Up ThunderX2 CPU (MPR)
After falling short of its promises regarding ThunderX, Cavium is doubling down on performance for its next-generation ThunderX2, which it expects to sample this year.
CCIX: Coherent Interconnect for All (MPR)
The new CCIX Consortium is developing an open standard for connecting processors with coherent GPUs, FPGAs, NICs, and other accelerators, particularly in the data center and for HPC.