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Current MPR Articles

December 10, 2018

  • Esperanto Maxes Out RISC-V
    The startup has developed a high-performance RISC-V CPU called ET-Maxion that it plans to ship in its first AI accelerator and also license to select customers.
  • PAM4 Drives Serdes to 100Gbps
    Data centers are on the cusp of 400G Ethernet adoption enabled by 100Gbps-per-lambda optical modules, which require PHYs with sophisticated signal processing. Six vendors are now sampling such chips.
  • Ambiq Apollo 3 Boosts Wearables
    Ambiq is using its initial success in Huawei wearables to improve its Apollo MCUs. Apollo 3 Blue adds features while reducing power compared with Apollo 2.

December 3, 2018

  • AMD Ships Industry’s First 7nm GPU
    By moving its Vega GPU architecture to 7nm, AMD boosted the performance of its Radeon Instinct cards, which support AI and scientific computing but not PC graphics.
  • TI Samples Its First 64-Bit Arm
    Texas Instruments’ new Sitara AM65x processors combine up to four Cortex-A53 CPUs, three real-time-control subsystems, two 32-bit Cortex-R5F microcontroller cores, and an optional GPU.
  • Renesas Focuses on ADAS Cameras
    A computer-vision processor for camera-based automotive systems, the Renesas R-Car V3H integrates the company’s hard-wired accelerators and custom vision DSP along with a programmable AI engine.

November 26, 2018

  • NovuMind Relieves Tensor Headaches
    The startup’s NovuTensor neural-network accelerator runs its compute engines at just 400MHz, but by combining hardware parallelism and time-division multiplexing, they deliver 15 trillion operations per second.

November 19, 2018

  • Intel, AMD Monsters Battle for HPC
    SC18 brought new server-processor disclosures from Intel and AMD. The former announced its 48-core Cascade Lake Advanced Performance while the latter disclosed new details of its 64-core Rome. 
  • Arteris Upgrades NoC for AI
    The new version of Arteris IP’s network-on-a-chip (NoC) intellectual property adds several upgrades, including features that help to design artificial-intelligence processors and other SoCs.
  • Imagination Cuts GNSS Power
    A new package of synthesizable intellectual property (IP) for integrating a low-power global-navigation receiver in SoCs, the Ensigma Series 4 takes “snapshots” to save energy when determining location.

November 12, 2018

  • SiFive Raises RISC-V Performance
    At the Linley Fall Processor Conference, SiFive revealed its 7 Series cores. The new CPU is its most complex yet, moving into the same class as Arm’s “little” Cortex-A family.
  • Editorial: AI Competition Begins to Bloom
    Several new vendors are challenging Nvidia’s performance lead in neural-network inference and training, including Cornami, Graphcore, Habana, Intel/Nervana, Wave, and Xilinx.
  • Wave Exposes Broad Roadmap
    Wave Computing is offering evaluation versions of its initial AI-acceleration systems while developing a second-generation ASIC, new MIPS cores, and its first licensable AI accelerators.

November 5, 2018

  • LS1028A Targets Cars and Factories
    NXP’s Layerscape LS1028A adds IEEE 802.1 Time-Sensitive Networking (TSN) and a graphics unit to its Ethernet controllers for mission-critical industrial and automotive applications.
  • Flex Logix Spins Neural Accelerator
    Known for its embedded-FPGA IP, the startup is developing the NMax inference engine, a licensable core that scales from 512GMAC/s to 74TMAC/s or more.
  • Cadence HiFi 5 Is a Smart Listener
    The new licensable DSP handles speech recognition in digital assistants and other devices with voice interfaces. Relative to HiFi 4, it doubles audio-DSP performance and quadruples inference-engine performance.
  • PowerVR Halves GPU-Memory Needs
    Imagination’s new PVRIC4 compression guarantees bandwidth savings of at least 50%, enabling designers to optimize their memory subsystem.
  • AIware3 Adds Rings to Neural Engine
    AImotive’s third-generation licensable engine for autonomous-vehicle neural networks employs a new configurable ring structure that can connect multiple compute units to boost performance.

October 29, 2018

  • Tachyum Tries for Hyperscale Servers
    The startup is developing a 64-core server processor, targeting tapeout late next year. The 7nm design implements a VLIW instruction set with custom vector and matrix instructions and a custom fabric.
  • Eta Compute MCU Puts AI in IoT
    The startup’s new Tensai chip combines an MCU with a DSP for machine learning. Eta completes its solution with optimized neural-network software for machine learning.
  • Editorial: NXP Drives to the Future
    Facing a future without Qualcomm, NXP will focus on its core automotive and industrial markets while de-emphasizing networking and mobile. Its new AI strategy focuses on software.

October 22, 2018

  • IBM Power9 Scales Up in Servers
    IBM’s Power9 processor for scale-up servers, now available on the merchant market, employs external memory buffers to offer leading bandwidth and capacity, plus up to 16-socket configurations.
  • Intel 9th Generation Adds Little
    Intel’s newest processors for gamers and content creators, Basin Falls and Coffee Lake-S Refresh, jump to eight cores in the Core i9-9900K but offer few other upgrades over the previous generation.
  • Arm Frees FPGAs to Use Cortex-M
    Arm is enabling free use of certain Cortex-M CPUs in Xilinx FPGAs, even for volume production. The new DesignStart FPGA program offers Cortex-M1 and Cortex-M3.

October 15, 2018

  • Turing T4 Targets AI Inference
    Nvidia’s new Turing architecture boosts AI inferencing performance by adding integer capability to its tensor cores. The Tesla T4 accelerator brings Turing to data centers as a 70W PCIe card.
  • Cadence Mutates Its DNA to Boost AI
    Cadence’s new DNA 100 IP core integrates a sparse-compute engine that supports applications ranging from low-power IoT devices to high-performance video surveillance and autonomous vehicles.
  • Titan IC Floats 100Gbps Reg-Ex Engine
    The company’s RXP core delivers leading regular-expression-search throughput for SoC designs and FPGAs. The primary application is in network-security appliances such as intrusion-detection systems and next-generation firewalls.

October 8, 2018

  • Turing Accelerates Ray Tracing
    An upgrade to the two-year-old Pascal, Nvidia’s new Turing architecture delivers a big performance boost, AI-enhanced imaging, and real-time ray tracing for PC and professional graphics.
  • Xilinx Versal Surpasses UltraScale+
    Scheduled to sample in mid-2019, Versal chips will combine Arm Cortex-A72 CPUs and new AI Engines with field-programmable logic, redefining FPGAs as full-fledged SoCs.

October 1, 2018

  • NRAM Brings Nanotubes to Silicon
    NRAM uses carbon nanotubes (CNTs) in silicon to offer DRAM-like performance and density with nearly unlimited endurance and retention. Products could reach production in 2020.
  • NetSpeed Disappears Into Intel
    Network-on-a-chip (NoC) vendor NetSpeed Systems is now part of Intel, giving it a good exit but leaving its customers without a roadmap and consolidating the NoC market.
  • Marvell Reveals Post-Cavium Roadmap
    As Marvell works to integrate its Cavium acquisition, it’s paring unneeded and overlapping product lines. The changes affect both Cavium and Marvell roadmaps.

September 24, 2018

  • CPU Performance for the Next Decade
    A comprehensive analysis of a decade’s worth of processor data reveals the approaches that have enabled CPU and GPU performance to double every two years and how they will change over time.
  • Fujitsu Raises Arm Over SPARC
    Fujitsu’s Post-K exascale supercomputer will bring Arm into the HPC world with its new 52-core A64FX, an extreme processor for an extreme machine.
  • Editorial: Intel Customizes Cloud Chips
    More than half of Intel’s cloud shipments are custom models that add or delete features from standard products. This approach satisfies customer needs while giving Intel pricing flexibility.
  • Marvell Connects SSDs to Ethernet
    Marvell is sampling the 88SN2400, a unique controller chip that connects an SSD to Ethernet, enabling a new storage-array architecture based on Ethernet instead of PCI Express.

September 17, 2018

  • Graphcore Makes Big AI Splash
    One of the best-funded AI startups is sampling its first product, an accelerator chip that packs 1,216 independent CPUs and matches the performance of Nvidia’s V100 at half the power.
  • DeePhi Accelerates Xilinx AI Strategy
    Xilinx recently acquired DeePhi, a developer of FPGA-based accelerators for computer vision and speech recognition, to add to its large library of reference designs that it can offer to its FPGA customers.
  • Broadcom First With 200Gbps NIC
    Broadcom is first to sample Ethernet adapters for new 50Gbps-per-lane standards, including 50GbE and 200GbE. The NICs use the new Thor controller chip, the company’s third-generation NetXtreme-E design.
  • Wear 3100 Boosts Smartwatch Life
    Qualcomm has added a real-time controller to its next-generation smartwatch platform, creating a big-small-tiny architecture that extends battery life for Wear OS watches.

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