Current MPR Articles
August 1, 2016
SiFive Offers RISC-V Platforms (MPR)
A startup founded by the creators of the RISC-V instruction set aims to reduce the cost of ASIC development by designing and selling custom chips based on open-source CPU cores.
Ceva X2 Controls Multiple PHYs (MPR/MCR)
Ceva’s new X2 DSP performs physical-layer (PHY) control in complex wireless modems such as LTE-Advanced, which requires control of multiple communications channels.
Fusion G3 Beefs Up Floating Point (MPR/MCR)
Cadence has developed the Fusion G3 DSP to target mobile and consumer applications, offering up to four times the performance of its Fusion F1.
July 25, 2016
Polaris Revitalizes AMD GPUs (MPR)
AMD’s 14nm Polaris architecture combines intelligent rasterization, quality of service, and novel circuit designs to nearly double performance per watt in the new Radeon RX 480.
Editorial: Intel Extends Server Control (MPR)
Initiatives such as XPoint memory and RSA give Intel more control of the server platform even to the rack level, improving its profits but hobbling its customers.
Guest Commentary: Be a HW and SW Engineer (MPR)
As the slowdown in Moore’s Law constrains hardware performance, software and hardware engineers must better understand each other’s disciplines to optimize performance.
ARM Hatching 4K Video Egil (MPR/MCR)
ARM is developing a new video core, code-named Egil, that includes enhanced HEVC (H.265) support as well as the ability to encode and decode Google’s VP9 format.
July 18, 2016
Andes N650 Targets Low-Power IoT (MPR)
Andes has developed a low-power area-efficient CPU core, the 32-bit N650, that further extends the low end of its lineup to target IoT clients with very low power requirements.
July 11, 2016
Xeon Phi 7200 Boots Up for HPC (MPR)
The initial Knights Landing products are now in production, delivering 3Tflop/s of double-precision performance with up to four times the power efficiency of Xeon E5.
In Memoriam: Michael Slater, Microprocessor Guru (MPR)
Michael Slater, founder of this newsletter as well as a friend and mentor to many of our staff, has passed away at the age of 60.
July 4, 2016
Synopsys Improves Vision With DSP (MPR)
The new DesignWare EV6x embedded-vision cores complement the ARC CPU with a 512-bit vector DSP and an optional convolutional-neural-network (CNN) accelerator.
Broadwell Accelerates the DPDK (MPR/NWR)
Intel Xeon processors are improving their networking performance through better hardware and better software—in particular, the Data Plane Development Kit (DPDK). Other vendors are following suit by adapting the DPDK to their processors.
June 27, 2016
IBM TrueNorth Tackles Deep Learning (MPR)
IBM’s neuromorphic processor tremendously improves power efficiency for certain machine-learning problems by eschewing the traditional memory model and relying on fixed-function computation.
Editorial: Learning Chips Hit the Market (MPR)
Google and IBM have already deployed custom chips optimized for deep learning, and several startups are also taking this approach, creating a new wave of microarchitecture design.
GPUs Stream Into Data-Center Xeons (MPR)
Intel’s new Xeon E3-1500v5 server processors accelerate video and graphics workloads, pairing four Skylake CPUs with a powerful GPU and a co-packaged eDRAM cache.
June 20, 2016
14nm Broadwell-EX Boosts Brickland (MPR)
The third socket-compatible processor in Intel’s Xeon E7 platform known as Brickland, Broadwell-EX boosts performance and power efficiency by up to 30% and doubles memory capacity.
High-End Mali Takes Bifrost Bridge (MPR/MCR)
ARM’s newest GPU architecture addresses the requirements of high-performance graphics and enables cache-coherent CPU/GPU operation for general-purpose-GPU (GPGPU) computing.
Marvell IAP220 Targets Smart Home (MPR)
The new IAP220 combines dual Cortex-A7 CPUs with a low-power sensor hub, making it well suited to Android-based IoT devices. It can also serve in smartwatches.
Sonics Ice-G1 Simplifies the PMU (MPR)
Sonics’ new power-management IP replaces the traditional microcontroller with a set of state machines that provide much faster and more-localized control, reducing energy consumption.
June 13, 2016
Mellanox Marries ConnectX to Tile-Mx (MPR/NWR)
The new Mellanox BlueField SoCs integrate the company’s ConnectX Ethernet adapter design with ARM Cortex-A72 CPUs and the Tilera multicore technology acquired with EZchip.
June 6, 2016
Cortex-A73 Improves Mobile Efficiency (MPR/MCR)
The new Cortex-A73 focuses on power and sustainable performance instead of benchmark scores, reducing power by 20% and die area by 25% compared with its predecessor
Cavium Beefs Up ThunderX2 CPU (MPR)
After falling short of its promises regarding ThunderX, Cavium is doubling down on performance for its next-generation ThunderX2, which it expects to sample this year.
CCIX: Coherent Interconnect for All (MPR)
The new CCIX Consortium is developing an open standard for connecting processors with coherent GPUs, FPGAs, NICs, and other accelerators, particularly in the data center and for HPC.
May 30, 2016
Mali-G71 Enables Coherent Computing (MPR/MCR)
ARM’s Mali-G71 enables full hardware cache-coherent operation for tightly coupled CPU/GPU workloads as well as TrustZone support for content protection.
Ncore Makes FlexNoC Coherent (MPR)
The new Ncore NoC intellectual property from Arteris enables easy creation of fully heterogeneous cache-coherent SoCs.
Nvidia Brings Pascal to the Masses (MPR)
Nvidia has launched the GTX 1080, its first consumer GPU based on the Pascal graphics architecture.
Cypress Adds WICED to IoT Lineup (MPR)
To expand its IoT efforts beyond microcontrollers, Cypress has acquired Broadcom’s line of integrated Wi-Fi, Bluetooth, and ZigBee processors.
May 23, 2016
Intel Exits Mobile as Atom Bombs (MPR/MCR)
Intel has canceled all future Sofia products as well as the Broxton processor, officially ending its efforts to become a leader in the smartphone and Android tablet markets.
X-Gene 3 Performance Piques Interest (MPR)
According to AppliedMicro’s latest simulations, the forthcoming X-Gene 3 will match the per-socket and per-thread performance of a high-end Xeon E5v4 processor at a similar power level.
May 16, 2016
Octeon Expands Market With ARM (MPR/NWR)
Cavium has extended its 48-core ThunderX architecture across a broad range of embedded processors, offering the new ARM-based Octeon TX alongside the MIPS-based Octeon III.
Broadcom Offers First 64-Bit StrataGX (MPR/NWR)
Broadcom has launched its first 64-bit StrataGX SoCs, which offer four Cortex-A57 CPUs and a host of accelerators for realizing virtual network functions.
NXP’s Cortex-A72 Quartet (MPR/NWR)
Four new QorIQ processors, including the octa-core LS2088A and quad-core LS2048A, combine ARM’s best CPU with NXP’s second-generation packet-processing hardware.
May 9, 2016
Nvidia Hits HPC First With Pascal (MPR)
Based on the Pascal architecture, the 16nm Tesla P100 GPU uses 56 cores to deliver 5.3Tflops double-precision or 21.1Tflops half-precision while burning 300W.
NXP Economizes With LS2080A (MPR/NWR)
NXP’s newest QorIQ processors, the octa-core LS2080A and quad-core LS2040A, bring lower-power and lower-cost options to the ARMv8-based LS2-series.
Editorial: AMD Goes to China (MPR)
AMD is the latest chip vendor to partner with a Chinese company, but similar partnerships have not worked out well for foreign companies that share their valuable IP.
Convertible PCs Sail on Apollo Lake (MPR)
Apollo Lake is Intel’s next-generation entry-level processor for PCs. The 14nm device, which integrates the new Goldmont CPU, succeeds Cherry Trail for mini PCs and 2-in-1 convertible tablets.