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Linley Newsletter

DRAM+CPU Hybrid Breaks Barriers

January 6, 2011

Issue #335

Author: Tom R. Halfhill

Radical Chip Design Slashes Power Consumption, Boosts Memory Bandwidth

Today's high-performance microprocessors are mostly memory, not logic. Of the 774 million transistors in an Intel Core i7-860 processor, for example, about 69% are SRAM transistors in the 8MB L3 cache. The balance weighs even more heavily toward memory in server processors with larger caches.

This wasn't always so. Thirty years ago, microprocessors didn't need caches, because DRAMs and even mask ROMs were fast enough to keep up with contemporary processors. Over time, processors outran external memory, prompting the integration of on-chip SRAM to cache frequently used instructions and data. Today, paradoxically, big caches are promoted as a feature, even though they inflate manufacturing costs, gulp power, and wouldn't exist if external memory was fast enough. Simply put, caches are kludges.

Now, a Texas-based startup, Venray Technology, is bucking the trend toward bigger caches--and the march toward bigger CPUs, too. Instead of building expensive six-transistor (6T) or eight-transistor (8T) SRAM cells in a logic process to accommodate the processor, Venray is moving the processor to commodity-DRAM processes, whose 1T memory cells are cheaper to manufacture and less leaky. Merging the CPU with DRAM dramatically boosts memory bandwidth, reduces memory latency, and slashes power consumption by eliminating caches and shortening the CPU-memory interface.

Venray is trying to exploit both semiconductor technology and semiconductor-industry economics. Commodity DRAM is ridiculously cheap: a 1Gb DRAM chip with one billion transistors costs about $1, whereas an Intel processor with the same number of transistors can cost $200 or much more. DRAM is more power efficient, too. Bit cells can't tolerate much current leakage without losing data, so DRAM transistors are built to leak less power than logic transistors. To prove its technology, Venray has designed a DRAM+CPU prototype.

Venray hopes that its intimate CPU+DRAM integration will revolutionize microprocessor design. As is usually the case, Venray makes several tradeoffs, including slower transistor switching, less sophisticated CPUs, and perhaps a useless surplus of memory bandwidth. But whether the venture succeeds or fails, an eventual merger of microprocessors and memory seems inevitable. In time, Venray's compromises may become easier to swallow than the alternatives.

Graphics with this article:

Figure 1. Venray's Aurora test chip.

Figure 2. Thread-Oriented MIcroprocessor (TOMI) block diagram.

Figure 3. Block diagram of Venray's "Shirtbook" tablet.

Microprocessor Report subscribers can access the full story (6 pages, 3 graphics) here:

http://www.mdronline.com/mpr/h/2010/1227/245202.html


Nonsubscribers can purchase individual copies of Microprocessor Report articles for $50 by contacting us.

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