Fujitsu and Oracle Ignite SPARCsSeptember 14, 2012
Author: Tom R. Halfhill
SPARCs flew at the Flint Center in Cupertino, the site of this year’s Hot Chips Symposium. SPARC makers Fujitsu and Oracle both lit up the stage with new server processors intended to defend the seminal RISC architecture against more encroachments by x86 and POWER chips. Whereas Fujitsu’s tenth-generation Sparc64 X design emphasizes per-thread throughput, Oracle’s Sparc T5 excels at multichip scaling.
The Sparc64 X introduces several new features that improve performance over its immediate predecessors, the Sparc64 VII, VII+, and VIIIfx. First, the new chip has 16 CPU cores—four times as many as the Sparc64 VII+ and twice as many as the Sparc64 VIIIfx. Although the existing Sparc64 IXfx supercomputer processor also has 16 cores, its CPUs are single threaded, whereas the Sparc64 X has an enhanced version of the dual-threaded cores found in the Sparc64 VII+.
The enhanced CPU core extends the SPARCv9 architecture to accelerate decimal math, cryptography, virtualization, and database processing. Improved function units accelerate integer operations and fused multiply-adds. Branch prediction is more accurate and out-of-order execution is more flexible. The instruction pipeline is deeper, permitting higher clock frequencies. Floating-point registers gain ECC protection, and an improved recovery mechanism automatically retries instructions interrupted by transient errors.
At the chip level, the Sparc64 X has new interconnects that can link up to four processors without the external glue chips and memory controllers required by the previous generation. The four embedded DRAM controllers provide nearly 4.5 times more memory bandwidth, and two PCI Express (Gen3) interfaces provide 16 I/O lanes through their integrated serdes. More than 53,000 error-checking circuits enable single-bit detection or correction for nearly every function on the chip.
Oracle’s Sparc T5 also has 16 CPUs, but it implements eight threads per core, versus Fujitsu’s dual-threaded CPUs. Moreover, the Sparc T5 now supports glueless multichip scaling to eight sockets, whereas its predecessor and the Sparc64 X gluelessly scale to only four sockets.
Both companies trumpet the high performance and reliability of their processors. It’s the main reason for designing their own chips (at considerable cost) instead of simply buying Xeon server processors from Intel like everyone else. Although a Xeon processor is probably more power efficient, it lacks the same features for RAS (reliability, availability, scalability).