Altera Reveals 20nm FPGA FeaturesSeptember 17, 2012
Author: Joseph Byrne
Having ushered its 28nm families into production, Altera isn’t popping a brewsky but is prepping its 20nm technologies. As it did before 28nm, Altera will use the newest fab process for its high-end parts (Stratix), but an older process for its low-end familly (Cyclone). The company has not revealed the process for new midrange Arria FPGAs or its SoC FPGAs that embed ARM CPUs.
In addition to enabling more FPGA gates on a chip, the 20nm process enables Altera to integrate faster serdes. The new FPGAs will have serdes running at about 40Gbps for chip-to-chip connections and also have 28Gbps serdes for board-to-board connections. A 40Gbps rate is not yet standard, but could be by the time Altera has its new FPGAs available. A future 56Gbps standard is likely, but may require 16nm technology before it can be implemented in CMOS.
Within the fabric, the major upgrade is to the DSP blocks. Altera has not provided details, but hints at changes to improve power efficiency. We expect functional improvements as well, even though the DSP block in the 28nm Stratix V was a major refresh. Design changes notwithstanding, the finer-geometry process enables more DSP blocks per chip and likely faster operation.
The third major capability Altera will introduce is multichip packaging (sometimes called 2.5D or 3D packaging) based on technologies such as silicon interposers and through-die vias. Pioneered for FPGA use by Xilinx in the 28nm generation, this type of packaging enables features infeasible with a monolithic die. Xilinx used the technology to create a monster four-die FPGA with 2 million logic cells compared with 1 million logic elements in Altera’s top-end 28nm part. Xilinx also used it to create a part with more 28Gbps serdes by putting the serdes on a separate die.
Altera isn’t a big believer in hiving off the serdes—after all, the I/O has to connect back to the serdes anyway—but is thinking up other uses for multi-die integration. One idea is to integrate a large monolithic memory. FPGAs have a lot of memory, but it is scattered throughout the chip. A 20Kb chunk is large in FPGA terms. A special DRAM with fast wide interfaces sitting on a silicon interposer could deliver much more bandwidth than a discrete memory. The DRAM industry would have to back such a design, but with rumors that Intel is considering using silicon interposers to put DRAM close to its processors, perhaps a standard is in the offing. Another use for multi-die packaging is to put an ASIC next to the FPGA. Stratix V integrated uncommitted blocks of Altera’s HardCopy gate-array technology, but supporting customers’ personalization of these blocks means spinning and qualifying a giant new FPGA die. The multi-die approach limits the changes to only the new logic and allows the customer to use a process other than a leading-edge 20nm one.
Altera did not announce specific products, which will come later. The company is trying to build excitement for its new technologies first. In another six months or so, we expect Altera to reveal details of the first of its 20nm chips.