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P5600 Extends MIPS Performance

October 29, 2013

Author: Tom R. Halfhill

Imagination Technologies is cementing its commitment to the MIPS architecture by introducing its first new CPU core since acquiring MIPS Technologies earlier this year. The P5600 is the first member of the Series5 Warrior family and is designed for consumer electronics, smartphones, tablets, and other high-performance embedded systems.

Unveiled at the recent Linley Tech Processor Conference, the P5600 is a licensable and synthesizable 32-bit CPU core with a 16-stage instruction pipeline, four-issue superscalar execution, instruction reordering, improved branch prediction, extended memory addressing, and hardware virtualization. Its 128-bit dual-issue SIMD units can handle single- and double-precision floating-point operations as well as integer data types. By pairing some operations, the P5600 can effectively issue up to eight instructions per clock cycle. A new coherence manager supports SMP clusters with up to six CPUs and a shared L2 cache. The P5600 also widens its internal data paths and external-I/O interfaces.

Although a 64-bit Warrior core is in development, Imagination is promoting the 32-bit P5600 for lower-priced smartphones and tablets—a market bifurcation that Apple has acknowledged with the iPhone 5C and iPad Mini. But even Intel is having trouble in these waters, having captured less than a 1% market share in smartphones despite years of trying. More likely, the P5600 and future Warrior CPUs will find happy homes in products already friendly to the MIPS architecture, such as broadband gateways, set-top boxes, and other consumer electronics.

Subscribers can view the full article in the Microprocessor Report.

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