Linley on Mobile
ARM Enhances Cortex-R ISANovember 19, 2013
Author: Kevin Krewell
Unlike previous years, ARM did not launch a new CPU core at its yearly developer conference, Techcon; instead it announced a new variation on the ARMv8 instruction set for real-time controllers. The Cortex ARMv8-R instruction set architecture (ISA) is based on the 32-bit portion of the ARMv8 instructions set, eschewing 64-bit functionality – at least for now. The new functionality includes a new privilege-execution support and support for an MMU that can support a rich operating system such as Android.
The announcement of an ISA without a corresponding CPU core echoes the original ARMv8 introduction two years ago; the company followed up the next year with new cores (Cortex-A57 and Cortex-A53). Although the first ARMv8-R processors probably won’t enter production before late 2015, ARM is introducing the new ISA now to start evangelizing software and system developers. The company already has a silicon vendor committed to the first product (under NDA), and the first ISA simulation models should arrive soon.
The new privilege model of the ARMv8-R is based on the simplified model used in Aarch64 mode in ARMv8. The new model lacks the PL-3 level for TrustZone. The new privilege-execution model is capable of supporting a number of scenarios as: multiple RTOS instances running on one microprocessor, a non-realtime rich OS running along with RTOS on the same microcontroller, and adding real-time determinism to a rich OS. An ARMv8-R CPU core can guarantee isolation between each OS using the underlying hypervisor under the MPU and MMU.
The ARMv8-R ISA runs the A32 and T32 (Thumb-2) ISAs from ARMv8, which includes new instructions such as load acquire and store release, as well as new cryptographic instructions. This latest ISA will enable cores that can blend the deterministic characteristics of the Cortex-R series with the performance and flexibility of the Cortex-A series.
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