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Sparc64 XIfx Uses Memory Cubes

September 23, 2014

Author: Tom R. Halfhill

In the never-ending race to build the world’s fastest supercomputer, using conventional technology is like running a 100-meter sprint in rubber boots. So Fujitsu’s newest Sparc64 processor laces up some wing-footed running shoes—such as Micron’s Hybrid Memory Cubes, new 256-bit vector instructions, and a pair of “assistant cores” that offload system software from the other 32 CPU cores. In fact, this is the first processor we’ve seen that uses Micron’s stacked-memory cubes.

Unveiled at the recent Hot Chips symposium, the Sparc64 XIfx is the latest in Fujitsu’s line of SPARC-compatible processors for high-performance computing (HPC). These devices have particularly strong FPUs and single-instruction, multiple-data (SIMD) extensions, which Fujitsu continues to improve. And the core counts are doubling with each generation. The new Sparc64 XIfx has 34 CPUs, including the two assistant cores. The previous Sparc64 IXfx (introduced in 2012) had 16 cores, and the Sparc64 VIIIfx (2011) had 8.

Packing 3.75 billion transistors, the Sparc64 XIfx is one of the world’s largest and fastest microprocessors. Built in 20nm high-k metal-gate (HKMG) technology, it runs at 2.2GHz and delivers peak floating-point performance of 1.1 teraflops. Overall, says Fujitsu, it’s about 3.4 times faster than its predecessor when running HPC applications.

Not a merchant product, the new Sparc64 XIfx will appear only in Fujitsu supercomputers. The company has withheld the die size, power consumption, cost, package details, and production schedule, but we estimate the chip measures 500mm2, consumes 200W (typical), and will begin production in 1H15. Using the new processor, Fujitsu hopes to build a system that can execute more than 100 petaflops—three times better than today’s fastest supercomputer.

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