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Kandou 500Gbps Serdes IP Targets 2.5D

September 12, 2017

Author: Bob Wheeler

Kandou’s new 16nm Glasswing hard macro enables 500Gbps interfaces between die in a 2.5D package. Like its 28nm predecessor (see MPR 3/30/15, “Kandou Narrows Focus to Serdes IP”), the new intellectual-property (IP) core implements the company’s CNRZ-5 protocol for 5-bit over 6-wire signaling. Whereas the older GW28-125-USR instantiates one such serdes, however, the new GW16-500-USR has four. Kandou is characterizing a 500Gbps test chip in its lab and plans to complete qualification of its IP by the end of the month.

The GW28-125-USR and GW16-500-USR both operate at 25Gbaud, or 12.5GHz. After coding overhead, CNRZ-5 yields 125Gbps of effective bandwidth at that baud rate. This approach compares with using five differential pairs, or 10 wires, to deliver the same bandwidth using NRZ coding. The first GW16-500-USR variant targets the TSMC 16FF+ process; Kandou says it will port the core to 16FFC in 4Q17. Because it’s intended for die-to-die connections in a 2.5D package, the core is designed for channels of only 24mm or less. This ultra-short-reach channel allowed the company to optimize for low power combined with a low bit error rate (BER) of 10–15.

The primary application for the GW16-500-USR is connecting a network ASIC die to a separate 56Gbps PAM4 serdes die (or “chiplet”). By separating most digital logic from the network transceivers, a chip designer can use leading-edge process technology (e.g., 7nm) for the former while using a lower-cost technology for the latter. For Kandou, the great advantage of on-chip interconnects is that they don’t require standards. The market is coming to the company, more than six years after its founding, through volume adoption of 2.5D packaging.

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