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Xilinx RFSoC Integrates Radio

October 24, 2017

Author: Bob Wheeler

Xilinx is sampling a new class of FPGAs that boosts integration by including high-performance analog-to-digital and digital-to-analog converters. The company calls these new devices RFSoCs; they join the Zynq UltraScale+ family of 16nm FPGAs, which previously included MPSoCs with integrated ARM CPUs. Compared with the shipping EG-series MPSoCs, the new chips add soft-decision forward-error-correction (SD-FEC) blocks as well as the ADCs and DACs, but they omit the ARM Mali-400 GPU.

The company targets multiple applications for the new chips, including remote radio heads (RRHs), baseband processing, and backhaul in wireless infrastructure; DOCSIS cable infrastructure in wired broadband; and radar/radio systems in military applications. To best match these applications, Xilinx will offer five different RFSoCs. The fully featured ZU28DR provides eight 12-bit ADCs operating at 4.0 billion samples per second (Gsps), eight 14-bit DACs operating at 6.4Gsps, and eight SD-FEC blocks. Other variants omit either the ADCs/DACs or the SD-FEC block, as some tasks require only one of these functions.

For programmable logic, the RFSoCs provide as many as 930,000 logic cells and 4,272 DSP slices. They also have up to 16x 33Gbps transceivers. Like their MPSoC counterparts, they integrate quad ARM Cortex-A53 CPUs plus dual Cortex-R5 CPUs for real-time tasks. High-speed interfaces include 100G Ethernet, PCIe Gen4, and DDR4 SDRAM.

Base-station OEMs often use FPGAs to implement the RRH digital front end (DFE), and these RRHs are increasing in complexity as the number of antennas grows. By integrating ADCs and DACs, Xilinx has simplified the system design while reducing interface power consumption. Its timing is nearly perfect, as the nonstandalone 5G New Radio (5G-NR NSA) specification is due in December. Customers can validate 5G-radio prototypes now, and the RFSoCs will likely reach production in time for early deployments in 2019.

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