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Flex Logix Spins Neural Accelerator

November 6, 2018

Author: Bob Wheeler

Flex Logix is jumping on the AI bandwagon with lofty performance targets. Known for its embedded-FPGA intellectual property (IP), the startup is developing the NMax inference engine, an IP core that scales from 512GMAC/s to 74TMAC/s or more. Although NMax has some configurable logic, the MAC arrays are hardened blocks, similar to DSP blocks. Flex will deliver the core with software that includes a new compiler, which generates RTL based on the characteristics of the neural network. By offering the new product, it’s moving “up the stack,” eliminating customers’ need to develop RTL code for its embedded FPGA. It expects to publish NMax specifications in 1H19 and tape out a chip in 2H19.

NMax builds on the tile structure the company already employs for its EFLX cores. The NMax512 tile incorporates eight systolic-array clusters, each instantiating 64 multiply-accumulate (MAC) blocks. Optimized for inference workloads, the MACs are configurable as 8x8 to 16x16, with the latter delivering half the maximum rate; they implement a 32-bit accumulator. The company expects the MACs to operate at 1.0GHz in TSMC’s 16FFC (or 12FFC) process, yielding 512GMAC/s per tile for INT8 data. The eight clusters are surrounded by the XFLX interconnect, which configures the data flow. Each tile additionally includes SRAM as well as FPGA (EFLX) logic for control and management.

NMax represents a strategic shift for tiny Flex, which has primarily targeted its eFPGA designs at networking, wireless-infrastructure, and aerospace/defense customers. Although the company is continuing to develop its EFLX4K cores, it’s directing resources into NMax development. By combining hard systolic arrays with FPGA data flow, the NMax design shows promise relative to processors that employ software-directed data flow.

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