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Wave Exposes Broad Roadmap

November 13, 2018

Author: Linley Gwennap

While working to finish its first product, Wave Computing is already planning a diverse roadmap to address AI acceleration in data-center, edge, and client devices. It disclosed at the recent Linley Fall Processor Conference a new roadmap, its first since acquiring MIPS Technologies. The roadmap features a next-generation processor design along with new CPU and AI cores for licensing.

Wave’s initial product is a “departmental appliance” that contains four DPU processors in a workstation-size box. The system runs Linux and supports neural networks through the ONNX API. Wave is now shipping evaluation systems that we expect will enter production early next year, but it is withholding prices and power consumption until general availability. The company is already working on a second DPU chip, which will use Broadcom’s ASIC flow in TSMC 7nm technology. Wave expects to pack 32,000 of its AI cores into the new chip, twice as many as on the initial 16nm design. Whereas the DPU1 uses Hybrid Memory Cube (HMC), the DPU2 will switch to the more popular High Bandwidth Memory (HBM).

For customers that want to develop their own AI-enabled SoCs, Wave will license its DPU cores, but only in combination with MIPS CPUs. Tapping its deep expertise in intellectual-property (IP) development, the former MIPS team is helping convert the initial DPU RTL into a licensable product while improving the software stack and development tools. Licensees can easily scale the number of DPU cores to achieve a wide performance range, depending on the area and power budget. The company won’t ignore the existing MIPS CPUs; it plans to continue developing and supporting both 32- and 64-bit CPUs for a range of end applications. We expect the first new cores from this program to become available in 2019.

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