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Intel, AMD Monsters Battle for HPC

November 20, 2018

Author: Bob Wheeler

In advance of this month’s SC18 (nee Supercomputing) conference, Intel announced a new class of Xeon Scalable processors and AMD disclosed details of its next-generation Epyc server processors (code-named Rome). Both companies are employing multidie packages to push core counts to new heights. Scheduled for a 1H19 release, Intel’s Cascade Lake Advanced Performance (CLX-AP) offers 48 cores and supports a 2S system configuration. AMD is sampling Rome, which scales to 64 cores and is socket compatible with shipping Epyc processors (“Naples”). We expect both products will reach production by mid-2019.

We wrote about Cascade Lake-SP after Hot Chips, but that processor delivers the same maximum core count and memory bandwidth as the first Xeon Scalable generation. To create the CLX-AP, we believe Intel uses a pair of 24-core die connected over UPI. The new processor has 12 memory channels—twice the number available in shipping Xeon Scalable processors. That change requires a new package, making the CLX-AP incompatible with the existing Purley platform. The company withheld clock speed, price, and TDP, but the TDP will certainly exceed the 205W of the hottest shipping Xeon.

AMD disclosed limited details of Rome, which is based on its 7nm Zen2 CPU design. Rome uses a “chiplet” approach, combining multiple 7nm CPU die with one 14nm I/O die. The company showed a 64-core chip that has eight CPU die surrounding the central I/O die. Although the Rome package is backward compatible with shipping Naples platforms, it adds PCI Express Gen4 support when serving in updated systems. AMD claims—rather broadly—that the 64-core version of Rome delivers 2x the same performance per socket as Naples and 4x the floating-point performance. The limited disclosures by AMD and Intel leave open the questions of leadership in performance per watt and performance per dollar.

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