Contributors: Bob Wheeler, Jag Bolaria, Joseph Byrne In This Issue
MIPS 74K Raises Performance Bar At last week’s Microprocessor Forum, MIPS Technologies revealed its newest licensable CPU core, the 74K. Using a 17-stage pipeline, MIPS expects to achieve the highest clock speed yet from a synthesizable CPU: 1GHz in a 65nm GP process. In comparison, ARM’s Cortex-A8 is rated at more than 1GHz in a semicustom implementation but only 850MHz in a synthesizable flow. The 74K features advanced architecture techniques normally found only in high-performance PC and server processors. In addition to issuing up to two instructions per cycle, the CPU can reorder instructions to avoid pipeline stalls. To compensate for potential branch delays caused by the long pipeline, the 74K implements a complex branch table that can predict branches with high accuracy. As a result, the CPU can sustain more than one instruction per cycle on many applications. In a 65nm process, the 74K core consumes less than 2mm2, versus less than 3mm2, for Cortex-A8, which is a dual-issue, in-order design. Thus, the MIPS design is both smaller and faster. MIPS, however, did not disclose power ratings for its CPU. Although the long pipeline and complex design increase power, MIPS says extensive clock gating and other techniques will mitigate this increase. Cortex-A8 is already sampling, whereas the 74K is just now available in final RTL, putting it several months behind the ARM design. The MIPS architecture is well established in consumer products such as set-top boxes, cable modems, and color laser printers. These applications place increasing performance demands on the CPU. The 74K provides a sizable performance upgrade while minimizing both hardware and software concerns. Broadcom has already announced plans to use the 74K, and we expect many others to follow. —Linley Additional coverage of MIPS-based products appears in our report A Guide to High-Speed Embedded Processors.
Earlier this month, Atheros announced a new slate of 802.11n chips, including the industry’s first 802.11n gateway processor family. Similar to the AR71xx processors Atheros introduced earlier this year, the new AR9001AP devices integrate a MIPS 24K CPU, Ethernet MACs, and audio and telephony interfaces. The new devices, however, add an 802.11n baseband/MAC and are available in various configurations to support different combinations of 10/100 vs Gigabit Ethernet, non-simultaneous dual-band operation, and 2x2 vs 3x3 MIMO. For the first time, Atheros also offers a 10/100 switch to round out its access-point chip set. The company gained this technology, as well as that for GbE, through its acquisition of Attansic in late 2006. We expect the cost-effectiveness of the new processors and the bundled switch will lead Atheros’s customers to switch their 11n designs from using switches and discrete processors from vendors such as Realtek, IC Plus, Intel, and Ubicom. The new products also position Atheros better against Broadcom and Marvell, the company’s main competition. Cost reductions will lower the price of 11n access points for consumers, accelerating adoption of the technology. Enterprise OEMs will favor discrete processors. Taking advantage of a recently announced testing regime for Draft 2.0 of 802.11n by the Wi-Fi Alliance, a few smaller OEMs have introduced 11n gear at the Interop show this past week. With the WFA assuring interoperability, enterprises have diminishing reasons to defer upgrading to the faster technology. Atheros also introduced an 11n client device with a USB interface, taking advantage of expertise gained from its 2006 acquisition of USB-WLAN specialist Zydas. Much like earlier Zydas reference designs, those for the new 11n client are relatively small—the size of a USB drive. Other chips announced include revised discrete MAC/baseband ICs and RF transceivers. Atheros claims the new devices deliver peak TCP throughput of 200Mbps per radio. The chips are sampling now, with production scheduled for 3Q06. —Joe Additional coverage of Atheros processors appears in our report A Guide to SOHO Gateway Processors. Seeking to take advantage of the transition to DOCSIS 3.0, much as it did with the transition to integrated voice, Texas Instruments disclosed its “Puma 5” cable-modem processor. TI plans to sample the chip in 3Q07, in time for the first round of DOCSIS 3.0 interoperability testing. Later in the year, the company will release more details about the chip. For now, we know it implements bidirectional channel bonding, IPv6, and AES encryption, per the DOCSIS 3.0 specification. Based on the latest iteration of TI’s gateway-processor platform, Puma 5 includes a programmable packet engine, a DSP for VoIP, and a high-performance MIPS CPU, possibly the new 74K. Channel bonding is the signature feature of DOCSIS 3.0, enabling greater bandwidth than DOCSIS 2.0 provides. Cable operators favor the new standard because it enables them to better compete against telcos’ optical networks. Additional coverage of TI’s cable-modem processors appears in our report A Guide to SOHO Gateway Processors.
In the fast-moving handset market, processor vendors must constantly update their product lines to deliver the right combination of integration, multimedia features, and air interfaces for each price point. “A Guide to Wireless Handset Processors" goes under the hood to examine these baseband and application processors and the vendors that provide them. Some of these processors are also used in PDAs and media players. You'll find in-depth coverage of Texas Instrument’s LoCosto, eCosto, and OMAP3; Qualcomm’s UMTS processors; NXP’s Nexperia platforms; Marvell’s PXA processors; LSI’s (formerly Agere’s) Vision products; Infineon’s E-GOLD and S-GOLD products; Freescale’s MXC and i.MX processors; and Broadcom’s updated Cellairity platform. We also cover baseband products from smaller vendors such as Analog Devices, EMP, Icera, Interdigital, MediaTek, and Spreadtrum as well as application processors such as Alchemy, Nomadik, and SH-Mobile. The report has been completely updated to include the newest announced products in this market. New in this edition is in-depth coverage of the emerging ultra-low-cost (ULC) market and the processors targeting this market. We also cover business changes, such as the six acquisitions of handset-processor vendors or business units in the past year, as well as significant new design wins and shifts in market share. We have updated the product plans for each vendor and our analysis of their future success. New in this edition are BDTI Certified benchmark results, based on the BDTI DSP Kernel Benchmarks and the BDTI Video Encoder and Decoder Benchmarks, for the most popular cores used in these processors. Whether you are looking for an innovative solution for your design, a vendor to partner with, or a rising company to invest in, this report will cut your research time and save you money. Get the inside scoop on this major market. Order “A Guide to Wireless Handset Processors” today. Order by June 30 to receive it at the prepublication price. For further details, visit our web site.
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