Editor: Linley
Gwennap In This Issue
Free Seminar! Join us on April 27 for a free one-day seminar on Fabrics and High-Speed Interconnects. This event, hosted by The Linley Group, IDT, StarGen, and Sandburst, will consist of a tutorial and three in-depth sessions. The seminar is free to qualified individuals who register early. For complete details and registration information, visit our web site. Freescale Supercharges Quicc Engine At Microprocessor Summit this week, Freescale announced the first PowerQuicc products to include the Quicc Engine, a new data-plane processor that replaces the classic CPM that has been the heart of the PowerQuicc line for 15 years. The Quicc engine features NPU-like hardware acceleration for functions such as classification, higher clock rates, a multi-CPU architecture, and Freescale's versatile communication controllers. It provides up to 1.2Gbps of interworking performance and 2Gbps of Layer 2 termination, a sizable improvement over the CPM. Naturally, Freescale has ported all previous CPM functions to Quicc Engine; furthermore, the company provides a new library of Layer 3 functions to complement previous Layer 2 CPM functions. In another significant departure from the CPM, Freescale will open the architecture for customers to program, using a new GUI-based development environment. The first Quicc Engine products will be a pair of secure PowerQuicc II Pro chips—the MPC8360E and MPC8358E—due to sample in 3Q05. The 8360E, which will list for around $45 in 10,000-unit quantities, includes a triple-issue e300 PowerPC core that operates at up to 667MHz, a 500MHz Quicc Engine, a 64-bit DDR memory interface, and a crypto engine that provides about 600Mbps of large-packet IPSec throughput. The 8358E, which lists for $35, supports clock rates up to 400MHz for both the e500 and Quicc Engine and provides a 32-bit DDR memory interface. Each processor is also available in a version that omits crypto acceleration. Unlike the single-processor CPM, the Quicc Engine can easily scale in performance by adding or removing CPUs. The initial products include two CPUs; we expect Freescale to ultimately revamp its entire PowerQuicc lineup using a single-CPU Quicc Engine in low-cost CPE products and multiple CPUs in metro/edge applications. The improved data-plane capabilities of the Quicc Engine will allow Freescale to compete directly against access NPUs such as Intel's IXP2350 (Westport) for high-volume applications such as DSLAM line cards. To be successful, however, Freescale must provide complete production-ready data-plane code for access applications. If Freescale is able to deploy the new Quicc Engine quickly across its product line, it will strengthen the PowerQuicc line and open up new applications. —SI Additional coverage of Freescale's PowerQuicc appears in our report A Guide to Communications Processors.
At last week's Intel Developer Forum (IDF), Intel revealed new network-processing acceleration techniques that will first appear in server platforms in 2006. Branded I/O Acceleration Technology (I/OAT), the new capabilities have been positioned as Intel's alternative to TCP offload engines (TOE). But from a hardware perspective, Intel is focusing on a different source of overhead--data movement. Although I/OAT will be first applied to Gigabit Ethernet controllers, the technology should easily scale to 10GbE rates. Due to enter production in 1Q06, the server platform code-named Bensley will be the first platform to include I/OAT. To reduce the CPU utilization associated with data movement, I/OAT uses a new form of DMA implemented by the system-logic chip set. In I/OAT, data is moved directly into the processor's L2 cache without using CPU cycles. The code-named Blackford system-logic chip set, which is used in Bensley, will implement the new DMA functions in its north-bridge chip while integrating a GbE MAC into its south-bridge chip. The new DMA feature will require network-stack changes, and Microsoft has pledged support for I/OAT in a future version of NDIS. I/OAT also takes advantage of Microsoft's receive-side scaling (RSS), which enables protocol processing to run on both cores of the dual-core CPU (code-named Dempsey) in Bensley servers. At IDF, Intel demonstrated its first complete Bensley prototype. Transferring 64KB blocks over a single GbE connection, I/OAT reduced CPU utilization from about 25% to about 11% of a single core. This demonstration also used Intel's "IA tuned" TCP/IP stack, and it is unclear if or when Microsoft will incorporate this tuned stack into Windows. Still, these very early results compare favorably with the performance of Broadcom's GbE TOE chip (CNIC), which works with Microsoft's TCP Chimney technology. I/OAT is a clear example of how Intel's new platform strategy enables architectural innovation. Now the question is whether or not OEMs will embrace such proprietary implementations. —BW Complete coverage
of Intel's GbE controller products appears in our new report
A Guide to Gigabit and 10G Ethernet Silicon. Our new report, A Guide to Gigabit and 10G Ethernet Silicon, Second Edition, is now available for immediate shipment. The report covers the newest switch, controller, and PHY chips for Gigabit and 10 Gigabit Ethernet. For more information, check our web site.
IDT recently introduced a family of PCI Express devices for bridging and switching. These devices target applications such as blade servers and storage subsystems. The products include two switch chips and two bridge chips. Fabricated on 0.13-micron technology, the switch products are scheduled to sample by 3Q05, and the bridge products are expected to sample in 4Q05. With three PCI Express ports each, the PES24N3 switch includes 24 lanes and the PES12N3 includes 12 lanes. Each port can be configured as x1, x2, x4, or (24N3 only) x8 lanes. One of the three ports may be used as a non-transparent port for greater scalability. Although PCI Express uses a single memory map, nontransparent bridging maps memory transactions between PCI Express domains to enable bridging between two hosts and their separate PCI Express trees. The switches use one virtual channel to provide quality-of-service (QoS) support. The PCI Express bridge chips include the PEB20N2 for bridging to 266MHz PCI-X 2.0 and the PEB20N1 for bridging to 133MHz PCI-X 2.0. These devices may be used for either forward or reverse bridging. With forward bridging, legacy PCI peripherals can be used in PCI Express platforms. In reverse bridging, PCI Express peripherals can be used in legacy PCI platforms. Each device provides transparent and non-transparent bridging. Although IDT is not the first vendor to offer PCI Express bridges, it has entered the market with aggressive pricing. Additionally it is the first vendor to announce a PCI Express bridge to 266MHz PCI-X 2.0. These devices include specific optimizations that should give IDT an advantage over its competitors. —JB Coverage
of PCI
Express products appears in our recent report A
Guide to High-Speed Interconnects.
Last week, PMC announced the 2Q05 sampling of a new access network processor, the PM7354. The 7354, which carries dual-redundant GbE interfaces and a 144-port Utopia 2 interface, provides interworking between ATM and IP networks and hardware features such as fine-grained traffic management and multicast for triple-play applications. Priced at $30 in 5,000-unit quantities, the 7354 requires an external control-plane processor such as PMC's MSP2006, priced at around $8 in volume. At a maximum power dissipation of only 3W, the 7354 nevertheless provides full line-rate interworking on its gigabit Ethernet interface, demonstrating the advantage of its hard-wired architecture. Access NPUs from Intel and Wintegra that provide comparable throughput are significantly more expensive and dissipate more power than the 7354 does; however, the 7354 lacks the flexibility of a fully programmable architecture. The PMC chip supports 576 queues, so it can handle 72 Utopia ports with 8 queues per port or 144 ports at 4 queues per port. Notably, multicast streams are turned into multiple unicast streams with individually selectable encapsulation per stream. By choosing a hard-wired design, PMC has taken a gamble. If the company has targeted the correct feature set for emerging DSLAM line-card applications, the 7354 will provide a compelling cost and power advantage against access NPUs in those applications; if not, the fixed-function chip will be difficult to sell at all. Infineon made a similar gamble with its Convergate-C product but lost. PMC's collaboration with some of its top-tier Asian customers in product definition makes it more likely that the 7354 will meet IP DSLAM design requirements for a large segment of the market. In that event, PMC will find that it has a winner in hand. —SI Complete
coverage of access processors appears in our report A Guide to
Access Processors. This week Vitesse announced LOVCAT192, a 10Gbps mapper targeted at Ethernet-over-Sonet applications. Rather than indicating feline affinity, LOVCAT stands for low-order virtual concatenation, which allows Ethernet to be cost-effectively transported over the existing Sonet infrastructure using flexible bandwidth allocation. With LOVCAT, Vitesse distinguishes itself as the first company to offer a family of 10Gbps mappers that perform low-order and high-order virtual concatenation. Compared to Vitesse's HOVCAT192, LOVCAT192 increases the number of virtual channel groups (VCG) from 64 to 128 and adds a SPI-3 interface. Although LOVCAT192 won't sample until 4Q05, Vitesse is committing to a mapper roadmap at a time when many vendors have stopped developing next-generation mapper products. —JB Coverage
of Vitesse's Ethernet-over-Sonet products appears in our report
A Guide to Next-Generation Sonet Silicon. The boom in storage area networks (SAN) continues due to the insatiable demand for storage combined with the shift from direct-attached storage (DAS) to managed storage. As SANs become larger and more complex, storage equipment vendors are adding more intelligence to their product to simplify their management. IP storage promises to reduce the cost of deploying a SAN, making it affordable for medium-size businesses that continue to use DAS today. While IP storage has been embraced by all leading storage equipment vendors, the requirements for high-speed TCP termination and iSCSI processing create new burdens. Storage processors from several startups use special-purpose architectures to meet these needs, but they have widely varying feature sets and integration. A Guide to Storage Networking Silicon provides up-to-date information on these products, how well they really work, for which applications they are best suited, and whether their vendors are likely to survive. It covers leading storage-silicon vendors Adaptec, AMCC, Aristos, Emulex, LSI Logic, PMC-Sierra, QLogic, and Vitesse as well as startups such as Aarohi, Alacritech, Astute, iStor, iVivity, and Silverback. The report also covers boards (HBA) as well as chips from these companies. Are you up-to-speed on the intricacies of storage networking, including SAN, NAS, and IP storage? We provide an overview of the key standards and technologies used in these applications, including Fibre Channel, SCSI, iSCSI, SAS, SATA, TCP, and IPSec. We cover what you need to know about Fibre Channel and SAS/SATA devices, describe the emerging category of storage processors, and project key technology and market trends, including the speed of IP storage adoption. Order by April 15, 2005 to get a special prepublication discount. For more information on this new report, including a preliminary table of contents, visit our web site.
If you missed Linley Gwennap at Embedded Systems Conference, where he moderated two session at Microprocessor Summit, check out his interview in the Tuesday Webcast. (Linley is about 5 minutes into the program.)
To receive The Linley Wire via e-mail, click here
|
