Editor: Linley
Gwennap In This Issue
Join us on April 27 in San Jose, CA, for a free one-day seminar packed with the latest information on Fabrics and High-Speed Interconnects. We've put together a program—featuring architects and CTOs from leading chip vendors—that is designed to educate system designers, equipment vendors, OEMs, VARs, and the financial community about the technologies competing in these markets. The seminar is free to qualified individuals who register by April 20. For a complete program listing and registration information, visit our web site. This event is sponsored by IDT, StarGen, Sandburst, Intel, and Xilinx.Agere Launches Access-Networking Chips Earlier this week, Agere announced the 2Q05 sampling of a pair of access-targeted devices, the APP300 network processor and the LLP link-layer processor, taking aim at multiprotocol processing in high-volume access applications such as DSLAMs and cellular-wireless equipment. Promoted under Agere’s new TrueAdvantage brand, these devices are complemented with production-ready firmware suites and software-customization services provided by Agere’s development partner, HCL. The APP300 is available in several variants, priced from $35 to $200 in volume quantities. High-capacity LLP devices are priced from $150 to $400; the lower-capacity LLP-W devices that target wireless, are priced from $50 to $150 in volume quantities. The APP300 is derived from Agere’s OC-48 NPU, the APP550. Like the APP550, the APP300 features a unidirectional, pipelined data path, combining several packet engines for classification, buffer management, and traffic management. These packet engines are programmable in a C-like language or, in the case of the classification engine, a proprietary high-level language. The APP300 reduces system cost by substituting DDR SDRAM for the APP550’s external FCRAM and integrating a 166MHz ARM9 control-plane processor. Delivering 2Gbps of throughput, the APP300 dissipates only 7W (or 4W for the slowest speed), thereby achieving leadership price/performance and power/performance ratios for access NPUs. The APP300 combines the low-power and high-throughput attributes of fixed-function devices with the flexibility of programmable devices; layered with Agere’s modular FPI software, the APP300 resembles a configurable fixed-function device to the system designer. The companion LLP, designed for framing and physical-layer functions in multiservice applications, combines several link-layer functions into one device: ATM AAL1 SARing, T1/E1 framing, HDLC, and IMA, and multi-link PPP. Interestingly, the LLP echoes the APP300’s design philosophy, combining an embedded CPU with fixed-function link-layer processors; but Agere does not enable customers to program the embedded CPU, instead providing an API to access embedded functions. The LLP’s programmable design means that Agere can release new firmware to add link-layer support for new protocols, for instance, PWE3. The LLP, which connects to the APP300 through a SPI-3 port, reduces system cost by replacing several discrete devices such as ATM SARs and IMA chips. This makes the LLP interesting in its own right; other NPUs can also attach the LLP to add support for link-layer protocols. Agere’s new access NPU is the latest evidence of increased competition in the access market. Wintegra set the bar for access NPUs with its scalable, low-powered WinPath family and application-targeted production firmware suites; Intel jumped into the fray with its IXP2350 (Westport), which leverages both the XScale control-plane processor and packet engines derived from its high-end NPUs; and Freescale announced a turbocharged Quicc Engine to elevate the throughput of its PowerQuicc processors to a multigigabit level. Agere’s NPU differentiates itself in this crowded market by offering better data-plane performance than WinPath, better I/O capabilities and lower power dissipation than Westport, and quicker time-to-market than the new PowerQuiccs. Although the APP300’s control-plane CPU is weaker than Intel’s XScale or Freescale’s PowerPC CPUs, the APP300 as a whole is appropriate for volume access applications such as line cards. With the APP550 available for higher-end applications, Agere is in the enviable position of providing a single NPU architecture that spans the gamut from 600Mbps to 5Gbps throughput. —SI Complete coverage of Agere’s NPUs appears in our report A Guide to Network Processors. Another new entrant in the access market is startup Ethernity Networks. The Israeli company has announced a new access processor, the MEA-LX, designed for IP DSLAMs and similar equipment. With throughput of up to 5Gbps, the chip integrates a set of proprietary packet engines that handle several Layer 2 and Layer 3 functions, including classification, forwarding, and traffic management for up to 256 virtual channels (VCs). The chip provides interworking between several protocols, including IP, ATM (AAL5), MPLS, PPP, and GFP. The MEA-LX also includes four Gigabit Ethernet MACs for the uplinks; it supports 48 ports of Fast Ethernet (SMII) for the downlinks, or a Utopia port can connect to external DSL chip sets. Because Ethernity has limited funding, and because it started with an intellectual-property business, the company has chosen to offer the MEA-LX in an FPGA rather than a fixed ASIC. Despite the FPGA implementation, the design is rated at 5Gbps and priced below $100, an attractive price/performance ratio. The FPGA model also provides the flexibility for Ethernity or the customer to customize the feature set of the chip. The startup may create an ASIC version of the device if it lands a large enough customer. Now that Ethernity has deployed a hardware solution, it must deliver the corresponding software to allow customers to easily create their own software to utilize the chip’s features. Although the startup is behind Wintegra and others in entering the access market, there may still be time to gain a foothold in this growing area, if Ethernity can deliver and demonstrate a complete hardware/software solution. —LG Complete
coverage of processors for access equipment appears in our
report A
Guide to Access Processors.
Everything you wanted to know about storage networking silicon but were afraid to ask. "A Guide to Storage Networking Silicon” provides up-to-date information on storage networking, including SAN, NAS, and IP storage. The report discusses Fibre Channel and SAS/SATA devices, profiles the emerging category of storage processors, and projects key technology and market trends, including the battle between IP storage and Fibre Channel as well as the battle between Fibre Channel and SAS/SATA. Learn how well these devices really work, for which applications they are best suited, and whether their vendors are likely to survive. The report covers leading storage-silicon vendors Adaptec, AMCC, Aristos, Broadcom, Emulex, LSI Logic, PMC-Sierra, QLogic, and Vitesse as well as startups such as Aarohi, Alacritech, Astute, iStor, iVivity, and Silverback. The report covers boards (HBAs) as well as chips from these companies. For those just getting up to speed in this market, we provide an overview of the key standards and technologies used in these applications, including Fibre Channel, SCSI, iSCSI, SAS, SATA, TCP, and IPSec. Find out which companies are leading this race and which ones have bet on the wrong horse. Order by April 15 to get a special prepublication discount. Visit our web site for more information.
Nikkei Electronics: NPUs Target Lower Cost
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