Editor: Linley
Gwennap In This Issue
Don't forget to order the new edition of "A Guide to Switch Fabrics" with the prepublication discount of $300. This offer expires at the end of May. Raza Discloses Powerful Processor, EoS Chip At Spring Processor Forum, stealth startup Raza Microelectronics (RMI) announced its much-anticipated multicore processor, known as the XLR. This powerful device contains eight MIPS64 processors operating at speeds up to 1.5GHz. Although it was announced only this week, the XLR has been sampling since December. Like most network processors, the XLR uses multithreading to improve the efficiency of its scalar CPUs while processing many packets in parallel. (David Hass, the XLR's architect, was formerly an architect at Nexsi, a failed NPU startup also funded by Raza.) Each XLR CPU switches among four threads, for a total of 32 threads on the chip. The XLR is the only commercially available MIPS processor to implement multithreading. Along with its high-speed CPUs, the XLR contains 2MB of cache memory and a crypto engine capable of 10Gbps of AES, 3DES, SHA-1, or MD5 encryption. It supports 12.8GB/s of peak bandwidth to DDR2 SDRAM or RLDRAM. The processor connects to the rest of the system through two integrated 10GbE MACs or four integrated GbE MACs as well as other high-speed interfaces. RMI quotes a list price of $850 for the high-end XLR but offers lower-cost versions with fewer CPUs and other restricted capabilities. The company positions the XLR for a wide range of control-plane and data-plane applications. The chip is well suited for high-end control-plane designs; compared with Broadcom's BCM1480, the XLR offers more CPUs, more clock speed, and multithreading for a lower price. We do not, however, expect the XLR to displace traditional NPUs from Layer 3/4 routing applications, due to the XLR's greater cost and power dissipation and incomplete software solution. Instead, we see the XLR competing with Cavium's Octeon in data-plane applications that require greater per-packet processing, such as security (intrusion prevention/antivirus), IP storage, and web switching. Octeon lacks the XLR's multithreading capability but offers a hard-wired DFA engine, useful in many security applications. At the same time, RMI also introduced its Orion chip, designed to provide packet service over the Sonet/SDH network. The Orion family includes products for OC-3, OC-12, or OC-48 Sonet rates and 8 FE ports, 2 GbE ports, or 3 T3/E3 packet ports. The Orion architecture consists of a Sonet/SDH mapper and an Ethernet interface. The mapper includes a Sonet/SDH framer, pointer processor, VCAT (virtual concatenation), LCAS, and GFP framer. The Ethernet interface includes MACs, MAC forwarding, and a traffic manager for 2K flows. The chip may be used for Ethernet over Sonet (EoS) or to switch Ethernet traffic. Although vendors such as PMC-Sierra and TranSwitch have been shipping data-mapping products for similar applications, RMI offers a highly integrated chip with sophisticated traffic-management capabilities that include dual-bucket policing, random early discard, and shaping. As a late entrant, RMI's challenge is to use Orion's unique features to establish a position in this nascent market. —LG/JB Complete
coverage of Cavium's Octeon and similar processors appears in
our report A Guide to High-Speed Embedded Processors.
Cortina Systems has announced availability of its second generation of RPR (Resilient Packet Ring) products. Cortina, a leading supplier of RPR silicon, already has design wins at Cisco and several major OEMs, including Extreme, Huawei, and Alcatel. At Cisco, the startup's technology is deployed in shared port adapters or I-Flex, which enable a single line cards for different networking protocols (ATM, Ethernet, Sonet). Madrid, the company's newest device, is a dual RPR MAC for applications such as ADMs, MSPPs, switches, and routers. Madrid enables TDM networks to be used for shared packet services with quality-of-service guarantees. It can also be used for failure protection and guaranteed service for packet networks in metro and enterprise networks. Madrid is a 10Gbps RPR device that terminates one RPR ring with two RPR channels, which can occupy any slice of the 10bps bandwidth. The device provides either a SPI-3 or a SPI-4.2 interface to enable 10Gbps and 2.5Gbps ADM/MSPP line cards. In these applications, Madrid would connect to an ASIC and Ethernet devices towards the line side and to a VCAT (virtual concatenation) framer towards the system side. For legacy applications, Madrid supports SRP—the precursor to RPR developed by Cisco. Madrid also integrates two GbE PHYs using TBI, which can connect to an external serdes device. The Ethernet interface allows Madrid to be deployed in applications that aggregate Gigabit Ethernet ports. Madrid uses SRAM to support enhanced bridging for up to 128 MAC addresses. This feature is useful for bridging between LANs without flooding MAC addresses. The device includes a mode to bypass the RPR processors and MACs for up to 64 channels. As some established vendors have cut back on Sonet and RPR programs, Cortina has continue to broaden its product lines. In 2004, it acquired Azanda for SAR and traffic-management capability and now claims design wins in more than 45 line cards. With limited competition and few new entrants, Cortina is well positioned to extend its business by reusing a combination of its RPR, Sonet, ATM, and Ethernet technologies. —JB Additional coverage of Cortina and other EoS devices appears in our report, A Guide to Next-Generation Sonet Silicon.
The new chips, due to sample in 4Q05, use the same PowerPC 440 CPU as the earlier 440GR and 440EP but boost the clock speed as high as 667MHz. They also add a Gigabit Ethernet port to the other peripherals already included in earlier family members and support the new DDR2 SDRAM standard. With pricing as low as $20 for the 440EPx, the new processors target multifunction printers, wireless access points, residential gateways, and other SOHO equipment. —LG Coverage of competing devices appears in our report A Guide to Communications Processors.
Join us on July 21 when The Linley Group hosts a free one-day seminar on access system design at the Marriott Hotel in Santa Clara. This event will be similar to our successful seminar on fabrics and high-speed interconnects, which was attended by more than 100 people. The access seminar will consist of four sessions. The first session, featuring The Linley Group analysts, will be an overview of challenges in packet processing for access-equipment designers and the various technologies available for solving these issues. The second session will describe and compare access-focused CPUs such Freescale’s PowerQUICC and AMCC’s PowerPC processors. The third session will cover access-focused NPUs such as Wintegra’s WinPath and AMCC’s nP3xxx. Each of these two sessions will include technical presentations from leading vendors as well as a moderated panel discussion. The seminar will conclude with a panel discussing the longer-term trend of converging CPU and NPU functions into a single chip. The event is designed to provide in-depth coverage of the most recent advances in access-system design presented by industry experts such as The Linley Group analysts as well as architects and chip designers from leading vendors. The event includes lunch and a reception to provide opportunities for you to network with these industry leaders, analysts, and your colleagues. This seminar is free to qualified individuals who register by July 15. The seminar is targeted at OEMs, VARs, press, and the financial community. Click here for further details and registration information. Event sponsored by Freescale, Wintegra, AMCC, and The
Linley Group.
We are now accepting proposals for presentations at the Network Systems Design Conference, which will be held in San Jose, California on October 18-20, 2005. NSDC will highlight the newest technologies and chips for networking applications. The only conference totally dedicated to network systems design, sessions will include technical disclosures of new networking chips as well as in-depth discussions on how to improve the design of networking equipment. NSDC focuses on technical presentations and on new disclosures. Proposals will be judged by the amount of new technical content (disclosed at the show or within the previous couple of months) and its significance to our audience. We are seeking proposals discussing network processors (i.e., chips that process packets) in all performance ranges and feature sets, NPU software and tools, communications processors, wireless LAN chip sets, storage processors, control-plane processors, security processors, classification coprocessors, search engines, and switch fabrics as well as interface, controller, and switch chips for Ethernet, Sonet, ATM, and Fibre Channel. Proposals may discuss standard products or in-house ASICs as well as techniques or technologies for using these products, however, preference will be given to commercial or commercializable technologies. We do not require that chips have reached first silicon, however, all presentations must include a significant amount of specific technical details about the product as well as an estimated availability date. Proposals should include the name of the device or system to be discussed, a general description of the device, a list of specific features that will be discussed in the presentation, the name and title of the presenter, and contact information for the person who should be contacted regarding the proposal. We strongly prefer presenters from engineering (e.g., chief architect, CTO) rather than marketing. In addition, the proposal should detail what information will be disclosed at NSDC 2005; for information that will be announced before NSDC 2005, please indicate when it is scheduled to be announced. The
deadline for submitting proposals is June 24, 2005. For more
information, or to submit a proposal, access
the NSDC
web site or e-mail
your proposal to program@networksystemsdesign.com.
The Linley Group is looking for a senior person to add to its analyst staff. The ideal candidate has both engineering design and marketing experience, able to discuss both the technical and business aspects of a product. Strong communications skills, both written and presentation, are required. Background in processors and/or networking is preferred. This position offers a unique vantage point on new technology developments across the networking-silicon industry. The Linley Group analysts are well known and respected. We offer the flexibility of a small company with health and retirement benefits. Compensation is commensurate with experience and ability. For more information, submit your resume to jobs@linleygroup.com. Principals only please. No agency candidates will be considered. No phone calls.
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