The Linley Wire
Independent Analysis of the Networking-Silicon Industry

Volume 5, Issue 13
July 7
, 2005

Editor: Linley Gwennap
Contributors: Bob Wheeler, Jag Bolaria, Joseph Byrne

In This Issue


Space is limited; register now to reserve your place! On July 21, The Linley Group will host a free one-day seminar packed with the latest information on the design of DSLAMs and other wireline- and wireless-access equipment. The program, presented by industry experts such as The Linley Group analysts as well as architects and chip designers from leading companies, is designed to educate OEMs, system designers, service providers, carriers, equipment vendors, and the financial community about the technologies competing in these markets. The seminar is free to qualified individuals who register by July 15. For a complete program listing and registration information, visit our web site.

This event is sponsored by Freescale, Wintegra, AMCC, Ethernity Networks, and The Linley Group.

Save the date! Mark your calendars for September 16 when The Linley Group, Cavium, Hifn, Freescale, Intel, and SafeNet host a free one-day seminar on Security System Design. Details on this event will be announced soon.

Freescale Developing PON-Integrated Processor

Last month, Freescale announced that it is developing a PowerQuicc processor with an integrated GPON interface that uses technology licensed from Alcatel. Although the company stopped short of making a product announcement, it appears that the processor could sample before the end of 2005.

Although PON (passive optical networking) deployment has been small when compared with DSL or cable modems, volumes are becoming sizable. PON cost-effectively enables many customers in a building or a neighborhood to share a high-speed optical connection. GPON, for example, delivers up to 1Gbps. PON is most popular today in densely packed areas in Asia, but it is starting to catch on in Europe and North America due to demand for IP-based video services.

Freescale plans to combine a PowerQuicc processor with its StarCore DSP on a single chip. Combined with Alcatel technology, the DSP will act as a GPON MAC. The chip will still require an external PHY and optical connection. Alcatel's contribution is based on its proven standalone GPON MAC, which is fully compliant with the G.984 standard. The PowerQuicc CPU can be programmed to provide voice, video, and data services and other residential-gateway functions.

As with other high-volume access technologies, integration is required to drive down the cost of PON for broad deployment. In the past, Freescale has lost high-volume design wins because it has been unable to integrate popular technologies such as DSL and 802.11 into its PowerQuicc processors. This time, the company is moving proactively to acquire and integrate crucial interface technology. This move should allow PowerQuicc to be a leading participant as PON volumes grow. —LG

Complete coverage of the PowerQuicc II family appears in our upcoming report A Guide to Communications Processors.


Tundra Samples Serial RapidIO Switches

In May, Tundra started sampling the industry's first serial RapidIO switch, the Tsi568A. With up to eight ports and a capacity of 80Gbps, the Tsi568A is targeted at wireless- and wireline-access equipment. Each port may be configured as a single x4 port or as two x1 ports. In the x1 mode, the Tsi568A allows for up to 16 ports. Complying with the RapidIO v1.2 specification, the Tsi568A can be used on a central fabric card or as a switch on a processor (DSP) card. The Tundra Tsi500 family also includes a lower power and smaller footprint version, the Tsi564A, which has a capacity of 40Gbps. Each switch chip integrates serdes and can route variable-length packets on the basis of priority.

Following the RapidIO specification, the Tsi568A supports four classes of traffic. The switch uses round-robin arbitration to select among same-priority packets targeting a single egress port. The Tsi568A includes data-integrity features such as CRC and acknowledgments. In case of a bad CRC on an incoming packet, the packet is discarded. The egress buffers keep a copy of the packet until the target sends an acknowledgment. These features provide guaranteed delivery by resending bad or dropped packets.

Freescale plans to include serial RapidIO in several of its PowerPC processors, and several DSP vendors have also endorsed the interface, creating a need for a switch that enables communication among these processors. We expect some of the leading cellular-infrastructure OEMs to use these processors and DSPs, providing a business opportunity for Tundra's switch. As the first vendor to sample a RapidIO switch, Tundra is in a good position to capture early design wins. —JB

Complete coverage of Tundra's Tsi500 chips appears in our new report A Guide to Switch Fabrics, 4th Edition.



News In Brief

This week, Wintegra announced that it reached profitability in the quarter ended June 30, 2005. The company achieved this milestone after a two-year revenue ramp as early customer designs reached production. Wintegra claims design wins in a variety of access equipment at nine of the top ten communications manufacturers. With this announcement, we believe Wintegra is positioning itself for an IPO later this year. Instead, partner PMC-Sierra could acquire Wintegra. But the price tag for such an acquisition is rising with Wintegra's improving financial performance. —BW

Last month, Crimson Microsystems came out of stealth mode by announcing Ruby, its first chip. The highly integrated Sonet/SDH chip includes framer, pointer processor, and crossconnect functions. Ruby can perform these functions for up to 16 OC-3/OC-12 ports or four OC-48 ports. Complementing the low-order and high-order path processing, the crossconnect has a capacity of 22.5Gbps for switching STS-1 and VT1.5 containers. Ruby's level of integration will be attractive for vendors developing micro MSPPs, where it replaces the equivalent of 2-5 components from leading vendors such as PMC-Sierra. —JB


Joseph Byrne Joins The Linley Group

The Linley Group is pleased to announce that Joseph Byrne has joined the firm as a senior analyst. With more than 15 years of industry experience, he is one of the industry's leading analysts covering the semiconductor market. Most recently, he was a principal analyst at Gartner, covering networking chips and other semiconductors. Before serving as an analyst, Joseph held consulting positions with Gartner, Deloitte consulting, and smaller firms in the U.S. and Europe. To learn more about Joseph, read his biography on our web site.

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