Editor: Linley
Gwennap In This Issue
If your design requires encryption or other security functions, don’t miss our September 16 seminar on Designing Security in Networking Systems. This one-day event features CTOs and architects who will describe system designs using the newest security products. Qualified attendees earn FREE admission, courtesy of our sponsors Hifn, Cavium, Freescale, Intel, SafeNet, and The Linley Group. For more information, access our web site. Cavium today announced sampling of its Octeon EXP family of multi-CPU processors. These devices are similar to the Octeon NSP devices announced earlier, but they do not include the encryption and reg-ex engines found in the NSP. Instead, the EXP devices combine 4 to 16 MIPS-compatible CPUs with two packet engines and a set of high-speed system interfaces. These processors are well suited to converged control- and data-plane designs at speed of up to 4Gbps. The CPUs can be partitioned in a variety of ways, depending on the application. For example, one or two CPUs can handle the control plane, perhaps running Linux or another embedded operating system, while incoming packets are spread across the remaining CPUs in parallel. This method allows performance to easily scale by changing the number of CPUs without changing the software. For applications that cannot execute on several CPUs in parallel, the software can be pipelined to take advantage of multiple CPUs. To support the CPUs, which operate at 600MHz, the EXP includes hardware for packet parsing, error checking, and TCP timers. A roomy 1MB L2 cache is backed by a memory controller that generates up to 8.5GB/s of bandwidth with DDR2-533 SDRAM. The chip connects to other devices using PCI-X, SPI-4.2, or its integrated Gigabit Ethernet MACs. At $350 for 4 CPUs or $650 for 16 CPUs, the Octeon EXP is a cost-effective solution for applications that demand high performance while running standard high-level software. Designers must be willing to optimize their software to run on multiple CPUs. We expect Cavium’s processor to be most successful in “high-touch” applications that perform extensive processing on each packet; these applications include content switches, wireless aggregation, and storage networking. —Linley Complete coverage of Octeon EXP appears in our report A
Guide to High-Speed Embedded Processors.
Texas Instruments today announced its sixth-generation cable-modem chip set, called Puma-4. The new device combines voice functions with a DOCSIS 2.0 interface and an application processor. Although TI ranks second in overall cable-modem chip shipments, the company is the leader for voice-enabled cable modems. Given the cable providers' growing emphasis on triple-play solutions, voice-enabled modems are expected to comprise more than half of the cable-modem market in 2006. Whereas most current systems use an external DSP for voice functions, Puma-4 integrates a complete DSP subsystem, greatly reducing the cost premium for voice. This DSP is based on TI's popular C55, leveraging the vendor's significant experience and investment in voice hardware and software. Puma-4 also includes a MIPS CPU that handles the upper layer voice protocols. TI provides firmware for a variety of low-bit-rate codecs such as G.726 and G.729. The chip also supports several cellular codecs, potentially eliminating transcoding for VoIP-to-cellular calls. TI plans to sample Puma-4 in 4Q05. The highly integrated processor also includes a complete DOCSIS 2.0 MAC and PHY, and it connects to a PC via Ethernet or USB. We expect Puma-4 will help TI continue to gain share against Broadcom as voice becomes more prevalent in cable modems. Puma-4 also provides a preview of TI's next-generation DSL-integrated processor, which we expect will be very similar except with a VDSL2 interface instead of DOCSIS 2.0. —Linley Additional
coverage of TI's residential-gateway chips appears in our
new report A Guide to Communications Processors. Intellectual-property vendor Rambus has added a PCI Express MAC to its successful PHY. This MAC handles the link and transaction layers of the PCI Express protocol. Rambus completed its PCI Express solution with the earlier acquisition of technology and 45 employees from GDA Technologies. Key customers for the PHY and MAC include PLX Technologies and Xilinx, respectively. With more than 40 licensees for its PCI Express PHY, Rambus is in a good position to secure licensees for its MAC. By matching a PHY and MAC that are optimized to work together, designers can reduce die size and power dissipation. Additionally, a single-vendor solution should reduce debug time. —Jag Additional
coverage of Rambus appears in our report A Guide to High-Speed
Interconnects. A new text
book, "Embedded Computing: A VLIW Approach to
Architecture, Compilers, and Tools" provides an informative
and lively examination of processor architecture and implementation.
Although it focuses on very long instruction word (VLIW) techniques,
the book also analyzes other high-performance techniques such
as superscalar, SIMD, and DSP architectures. Authors Josh Fisher,
a VLIW pioneer, Paolo Faraboschi, and Cliff Young take a holistic
hardware-software approach to the often-neglected area of embedded
computing. Network Systems Design Conference continues to focus on the critical issues that system designers are facing in their next-generation designs. We have reworked the program this year with sessions that are aligned with particular market segments. For example, broadband infrastructure is a fast-growing market, so we have added a session discussing and comparing the newest products for next-generation broadband technologies such as PON and VDSL2. Another session focuses on the metro market, covering products for Metro Ethernet and Ethernet-over-Sonet. Other sessions cover security systems, data-center equipment, and another emerging technology, WiMAX. Another set of sessions covers key technologies that cut across system categories, addressing the needs of many designers. This year's conference includes sessions on high-speed processors, switch fabrics, and high-speed interconnect. These sessions cover the latest trends, including multi-CPU processors, standard backplanes, and 10Gbps interconnect. These sessions include the newest technologies and devices, representing a leap beyond current products. If these topics interest you, NSDC is the must-attend show of the year. It is the only conference that focuses exclusively on networking system design, so you can quickly find everything you need in one place. You won't hear any recycled sales pitches, just straight technical talk from CTOs and architects that design real products. This year's program includes more than a dozen new company,
product, and architecture announcements you won't hear at
any earlier
show. NSDC is also a great place to meet with colleagues
and industry leaders, so you can swap stories or get
input on your
latest design issue. Whether you want to find the right chip
for your design, partner with a chip vendor, or invest in
a networking silicon company, Network Systems Design
Conference
is the place
to be on October 18–20. For more information on the
program and the conference, access the NSDC web site.
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