The Linley Wire
Independent Analysis of the Networking-Silicon Industry

Volume 5, Issue 21
November 10
, 2005

Editor: Linley Gwennap
Contributors: Bob Wheeler, Jag Bolaria, Joseph Byrne

In This Issue


P.A. Semi Targets Comms Market

At last month's Fall Processor Forum, secretive startup P.A. Semi disclosed that it is developing a family of PowerPC processors targeting communications and other high-performance embedded applications. The initial PWRficient processors, due to sample in 2H06, will include up to two 64-bit CPUs operating at up to 2GHz each. The startup, led by CEO Dan Dobberpuhl and CPU architect Jim Keller, is designing a custom CPU to deliver this high performance within a moderate chip power budget of 5W to 13W. Dobberpuhl and Keller previously drove the development of the SiByte processor family both before and after it was acquired by Broadcom, and they also worked together on Alpha processors at DEC.

P.A. Semi chose to license PowerPC for its new CPU, becoming one of the few companies to design a PowerPC chip. This exclusivity differentiates the startup from the hordes of MIPS suppliers while offering compatibility with a large range of networking and communications software. Although SiByte's choice of MIPS was largely driven by Cisco's IOS software, Cisco has more recently ported IOS to PowerPC. P.A. Semi was also widely rumored to have pitched its processor to Apple for use in notebook computers, but Apple's decision to switch to Intel processors has eliminated that opportunity.

In addition to its dual CPUs, the first PWRficient processor will integrate an array of useful system functions, including level-two cache, memory controllers, and high-speed interfaces such as PCI Express, Gigabit Ethernet, and 10G Ethernet. The architecture also includes offload engines for TCP, iSCSI, RAID, and encryption. This architecture should be well suited to several high-performance networking applications, including security equipment, storage controllers, SAN switches, networking control-plane and services cards.

At 13W for two 2GHz CPUs, the PWRficient chip appears to have better performance per watt than the PMC-Sierra RM11200 (2 CPUs, 1.8GHz, 15W) and other high-end processors that are available today in 90nm and 130nm technology. Some of P.A. Semi's power advantage, however, is likely due to its use of next-generation 65nm technology, and by the time PWRficient samples next year, competitors may have released improved products. We must also wait to see whether the new startup can deliver on its claims. At this point, however, P.A. Semi looks to be a strong new competitor in the high-performance embedded market, with a design that is well suited to networking and communications applications. —Linley

Complete coverage of the high-speed embedded market appears in our report A Guide to High-Speed Embedded Processors.


TranSwitch Discloses Envoy XE

At last month's NSDC, TranSwitch disclosed details of its Envoy XE. Envoy XE performs Ethernet and MPLS packet switching and is targeted at multiservice provisioning platforms and MxU access switches. The chip provides 8Gbps of bandwidth over a 4Gbps SPI-3 interface, two Gigabit Ethernet ports, one Fast Ethernet port, and three groups of Ethernet ports that can each be configured as eight FE or one GbE ports.

In addition to basic switching, Envoy XE also has a configurable parser and classifier to associate packets on ingress with 2K flows and four classes of service. The chip also performs policing and traffic management. Statistics and policing engines assist marking packets per MEF and IETF trTCM specifications. The device has four queues, corresponding to the four classes of service supported by the classifier, for each of the device's 75 ports. A traffic management engine performs multicast replication and drops or dispatches packets based on WRED and WRR congestion management and scheduling schemes.

Combined with TranSwitch's Ethernet-over-Sonet mappers, Envoy XE provides a complete Layer-2 solution for systems aggregating customer-facing Ethernet links to service-providers Sonet rings. Dissipating only about 4W (typ), it's a low-power alternative to NPUs. —Joe


ATCA Survey Results

In our last issue, we surveyed our readers' interest in ATCA. An impressive 58% said they are working on ATCA systems, and another 24% said they plan to in the future. It is possible, however, that many people who are not working on ATCA did not bother to respond to the survey. Of those responding, 53% said they were using Ethernet on the backplane rather than more exotic technologies. Surprisingly, RapidIO ranked second at 27%, well ahead of ASI at 11% and other technologies. We thank those of you who participated in our survey!

Coverage of RapidIO and ASI appears in our report, A Guide to High-Speed Interconnects.


News in Brief

Also at NSDC, Exar announced a universal OC-48 Sonet/SDH framer. Like some competing Ethernet-over-Sonet framer/mapper chips, EXtendAR 48M supports GFP, high- and low-order VCAT, and LCAS as well as PPP and ATM. The chip is unique, however, in also integrating 48 DS3 framers. The XRT95L53 EXtendAR 48M is priced at $695 in 1,000-piece quantities. —Bob


Report Highlights: A Guide to Access Processors

Now in its 2nd edition, "A Guide to Access Processors" has been extensively revised to bring you the very latest developments in the VoP and Access NPU market — including recent announcements made at Network Systems Design Conference.

Here are just a few of the many highlights you will find in this edition:

  • First-time coverage of Wintegra's second-generation access NPU, now at twice the performance.
  • A sneak peak at a high-density voice processor from a leading chip company.
  • First-time coverage of Agere's APP300 family of NPUs designed for a broad range of access applications.
  • Detailed description of the AMCC nP3705, AMCC's soon-to-launch entry into the access market.
  • The only public description of the chip that Broadcom won't talk about: an "off-the-menu" access NPU.
  • First-time coverage of Ethernity's unique configurable design for access network processing.
  • Detailed analysis of the first NPU that TranSwitch has brought to market.

Get up to speed quickly on the latest positioning of products and vendors in this important market. We separate the fact from fiction and provide the technology analysis you need to make informed business decisions.

Order by November 15 to get a special prepublication discount. For more information on this new edition, visit our web site.


New Report: A Guide to Network Processors

With the market for network processors now exceeding $150 million in annual revenue, products are becoming more specialized for their target applications. In recognition of this trend, we are evolving our coverage to better align NPUs with specific applications. Now in its seventh edition, "A Guide to Network Processors" has been revised to focus on the mid-range (OC-48) and high-end (10–40Gbps) NPUs typically used in metro applications. The report also covers configurable packet processors that compete with NPUs for metro-Ethernet designs. Low-end NPUs, operating at 2Gbps or less, are now covered in "A Guide to Access Processors" (see above).

In addition to expanded coverage and extensive updates of products and vendors, this edition includes new quantitative market data including NPU-vendor market shares for 1H05, market segmentation by performance/application, and a forecast through 2008.

Only The Linley Group follows this industry closely enough to give you a real-world view of this market. Which major vendors are in this business for the long haul? Which startups will survive and which will fail? How do the latest products stack up? "A Guide to Network Processors" is the result of years of research that cannot be matched. If you are interested in following this emerging standard-product segment, you have located the definitive source.

Order by December 15 to get a special prepublication discount. For more information on this new edition, visit our web site.

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