Editor: Linley
Gwennap In
This Issue
A Guide to Network Processors is now available for immediate delivery. Get up-to-speed on the latest developments in NPUs designed for metro applications. For more information, visit our web site. After Consolidation, NPU Market Fragments in 2005 Looking back on our early coverage of the network-processor market, I found a list of 30 companies that were developing or selling NPUs in 2000. Today, only four of those companies—AMCC, Intel, Agere, and Wintegra—are generating significant NPU revenue while investing in new designs. A fifth company, Hifn, did not appear on the original list but has since acquired IBM’s NPU business. After all this consolidation, however, no vendor ceased development of NPUs in 2005. We estimate NPU revenue was $174 million last year, enough to keep a handful of vendors interested in the market. Despite the modest size of the NPU market, the recent trend
in this market has surprisingly been segmentation. Vendors
are discovering
that a single general-purpose network processor cannot meet
the needs of a broad set of applications. New products,
and even
some vendors, now focus on a single segment: access, metro,
or enterprise. Once expected to be a huge opportunity for NPUs, enterprise routers have largely remained ASIC-based. Hifn is instead pursuing security applications using a combination of its encryption technology and IBM’s NPU architecture. This strategy fits Hifn’s expertise but steers it away from the mainstream NPU market. With little penetration in core routers, most other NPU vendors are targeting the metro segment. For example, startups EZchip, Sandburst, and Xelerated have integrated 10GbE MACs into their NPUs to better fit them into metro Ethernet equipment. These products are bumping into high-end switch chips from Broadcom, Marvell, and Greenfield that also target metro applications. This specialization trend makes it difficult for NPU vendors to be profitable, as they must either invest in multiple products or draw revenue from only one segment of the market. In 2006, Agere and/or Intel may decide to focus their NPU development exclusively on the access market in an effort to make their NPU businesses profitable. Even with further revenue growth in the coming year, the NPU market will continue to be challenging for the remaining vendors. —Linley Complete coverage of NPUs appears in our new reports A Guide to Network Processors and A Guide to Access Processors.
Last month, AMCC jumped into the GPON market with the introduction of the S3157PBI transceiver for customer premises or ONU (optical network unit). The S3157 perform serial-to-parallel conversion between the GPON interface and the system interface. The chip's 16-bit system interface can connect with an FPGA or an ASIC. Packaged in a 196-pin PBGA, the device has a typical power dissipation of 650mW and has been sampling since 3Q05. This transceiver arrives just in time for GPON plug fests scheduled for later this month. Already a supplier of EPON transceivers, AMCC extends its investment into GPON with this transceiver and plans to offer GPON controllers in the future. For a more cost-effective solution, AMCC is likely to integrate its transceiver and controller into a single device. —Jag Complete coverage of PON chips from AMCC and others appears in our new report A Guide to Next-Generation Broadband Interface Chips.
The Linley Group has lined up a great group of speakers to kick off its Linley Tech 2006 seminar series. On January 25, the topic will be CPU cores and intellectual property for networking and communications ASICs and SoCs. Featured speakers include Ashish Dixit, VP of Hardware at Tensilica; Mark Naumann, a SoC architect at Freescale; Peter Wells, a senior architect at ARC International; Michael Sobelman, a director of architecture at Rambus; and Egied Bormans, director of product management at SafeNet. The seminar will begin with an overview from Linley Gwennap, principal analyst at The Linley Group, discussing the advantages and disadvantages of IP licensing, the types of IP available for networking designs, and some background on CPU core technology. The second session will focus on CPU cores and how they can be used in communications applications. The third session will cover other networking IP such as encryption, 10G Ethernet, PCI Express, and high-speed serdes. We will end the day with a panel titled "Pitfalls and Pratfalls of Licensed IP." This Linley Tech seminar will be held at the Doubletree Hotel in San Jose. Regular admission is $495, but OEMs and chip designers can qualify for free admission, courtesy of our sponsors Freescale, SafeNet, Tensilica, and ARC International. Don't miss this opportunity to network with industry leaders and your colleagues. Get the information you need to solve your current design challenges. Sign up today at The Linley Group web site.
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