Editor: Linley
Gwennap In
This Issue
Intel Spins IXP28xx Network Processors Last month, Intel formally launched new versions of its IXP28xx network processor. In production since 4Q05, the new chips offer a choice of cooler or faster operation. The IXP2805 replaces the IXP2800 for new designs, while the IXP2855 is the new version of the security-enabled IXP2850. Aside from differences in core voltage at some clock speeds, the new chips are pin compatible with their older counterparts. Although the new chips remain in the same 130nm process, Intel claims the IXP28x5 consumes 20% less power than the IXP28x0 at 1.4GHz. The improved design also allowed Intel to add a new 1.5GHz speed grade, which dissipates 26W (typical) in the 2805 flavor. In conjunction with the IXP28x5 introduction, Intel discontinued the original dual-IXP28x0 development platforms in favor of its newer ATCA-based single-NPU designs. This change leaves Intel without a 10Gbps-capable development platform. The IXP28x5 chips are a step in the right direction, as they help address the thermal-design challenges associated with the IXP28xx. Because they are drop-in replacements for the IXP28x0 NPUs, however, they do not address other shortcomings, such as the chips' packet-interface limitations. Thus, the IXP28x5 makes life easier for existing customers but does little to improve Intel's competitiveness for new NPU-based designs. —Bob Complete
coverage of Intel's IXP28x0 NPU appears in our recent report
A Guide to Network Processors. Teknovus recently announced availability of its TK3713 EPON chip for optical networking units (ONU). This product bridges between 802.3ah EPON and Ethernet in addition to performing traffic management and classification. The TK3713 includes an EPON MAC, two Ethernet service ports, and a line-rate 802.1D bridge. For the EPON interface, this chip integrates the serdes for Gigabit Ethernet. For the service ports, the TK3711 includes one FE MAC and one GbE MAC. The TK3713 classifies packet traffic using Layer 2, 3, and 4 fields. The 802.1D bridge switches traffic among the service ports and EPON port. The TK3713 complements the company's OLT chip and enhances its earlier ONU chip. These enhancements allow Teknovus to compete with Passave for design wins at NTT, Japan's largest service provider and the biggest customer of EPON in the near term. Teknovus was the first vendor to offer multiple LLIDs (logical link ID) per ONU, enabling IPTV (as evidenced by KDDI in Japan). This new ONU chip increases the number of LLIDs from 3 to 8. The TK3713 is also in an easier-to-work-with PQFP package, instead of the BGA used by the company's earlier chip and by competing products. The new chip integrates FEC and bidirectional encryption, while many competing solutions as well as Teknovus's earlier products provide downstream encryption only. Compared to Passave's ONU chip as well as Teknovus's earlier chip, the TK3713 integrates memory to reduce external components and cost of the system. This integration results in a smaller footprint for the ONU as well as lower power dissipation. Teknovus estimates that the TK3713 enables OEMs to sell ONUs for about $60, and the chip helps reduce power dissipation from 6W in current ONUs to 2.2W. These improvements are helping Teknovus win designs in Asia and should get the company noticed by vendors, such as Mitsubishi, who are supplying ONUs to NTT. —Jag Additional
coverage of Teknovus products appears in our recent report
A Guide to Next-Generation Broadband Interface Chips. Erstwhile PowerPC collaborators IBM and Freescale have hooked up again. Freescale has joined Power.org, the consortium dedicated to developing the Power/PowerPC community. As the company that supplies most PowerPC processors, Freescale is an important addition to the organization. Our further analysis of this announcement is available in a white paper at: http://www.power.org/news/articles/freescale/PowerBackgrounder_tlg.pdf In other Power-related news this past week, IBM provided hints about its Power6 server processor, and Freescale and STMicroelectronics announced a joint venture. At ISSCC, IBM described elements of Power6 operating at about 5GHz. An earlier Power server processor, Power4, led to the PowerPC 970, one of the fastest processors available to embedded system designers. The Freescale-ST venture will create PowerPC microcontrollers for automotive applications and brings another major semiconductor company into the Power Architecture community. The pairing would be more exciting if the two companies were to collaborate on next-generation IP-based consumer electronics. The combination of ST's expertise in consumer electronics and Freescale's expertise in communications could lead to interesting products. —Joe Additional coverage of Freescale's PowerPC processors appears in our report A Guide to Communications Processors. Texas Instruments recently announced a new high-density voice-over-packet (VoP) processor. As with TI's earlier VoP processors, the new chip is bundled with software to create a complete solution. Unlike the earlier designs that used C55x DSPs, the new design is based on TI's C64x+ core. Design details and a product name have yet to be released; based on TI's claim of "3GHz of performance," we believe the chip to be a four- or six-core design. The C64x-based chip supports 200 adaptive multirate channels, about three times that of TI's previous top-end VoP processor, the C55x-based TNET3010V. This performance level puts TI ahead of key competitor Mindspeed, but we expect Mindspeed to counter with a new chip in 1H06. —Joe Additional coverage of TI's VoP processors appears in our report A Guide to Access Processors. Last week, MIPS Technologies disclosed a new CPU core that is the first to implement the company's multithreading extensions. The 34K CPU core can implement up to five threads, but the actual number is configurable at design time. Each thread adds only 5% to 10% of the core die area, resulting in a modest cost impact, but the performance gain can be quite significant, especially for applications that are memory-bound. For example, simulations show a 60% performance improvement on EEMBC benchmarks using only two threads. Multithreading is used in many proprietary network processors today; this new announcement makes it possible for chip vendors to add multithreading to their products without designing their own CPU. —Linley
Bob Wheeler, senior analyst at The Linley Group, will begin the program with an overview of switch/router design trends. The second session will focus on Control-Plane CPUs, how they can be used in control-plane applications, and what advantages each CPU provides to the system designer. The third session will cover data-plane technology, examining the building blocks and component technologies for advanced data-plane designs. The final session will focus on metro packet processing, covering leading NPUs and their application in metro networks. This Linley Tech seminar will be held at the Doubletree Hotel in San Jose. This seminar is free to qualified individuals who register by March 24. The seminar is targeted at system designers, service providers, carriers, equipment vendors, OEMs, press, and the financial community. Event sponsored by Freescale, AMCC, EZchip, Xilinx, Hifn, and The Linley Group. See our website for further details and registration information.
Principal analyst Linley Gwennap will give an overview of semiconductor
IP cores for networking chips as part of SafeNet's upcoming webinar
on Security in Silicon. This webinar will be available on March
15 at 1PM Eastern / 10AM Pacific time. For more information on
this webinar and how to attend it, access
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