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Reserve your place now for the Linley Tech seminar on High-Speed Interconnects and Fabrics to be held June 14. This seminar will deliver a market overview, in-depth technical presentations, and panel discussions. The seminar is free to qualified individuals who register early. For complete details and registration information, visit our web site. Sponsored by AMCC, Freescale, StarGen, Tundra, PLX, IDT, Dune, Pericom, and The Linley Group. Freescale today popped the hood on its Quicc Engine, promising that any Joe with a monkey wrench will be able to write code for the new packet engine, although initially only professional mechanics will be allowed in. The Quicc Engine, which is sampling today as part of the PowerQuicc II Pro processors, will eventually displace the popular but aging CPM in all of Freescale's PowerQuicc parts. For the older parts, customers can program the PowerPC CPU but not the CPM, which is a microcoded data-plane engine. The RISC-like design of the new Quicc Engine makes it easier for Freescale to allow full access to the data plane. Freescale still plans to provide a broad set of firmware for the Quicc Engine, including traffic management, QoS functions, and many Layer 1-3 protocols. But for customers who need an unusual protocol, a proprietary extension, or a differentiated data-plane feature, the company is developing a complete set of software-development tools for the Quicc Engine. These tools--which include a compiler, simulator, profiler, and graphical flow analyzer--will be integrated into Freescale's popular CodeWarrior Development Studio, which is used to develop PowerPC code today. Thus, users will be able to develop and debug PowerPC and Quicc Engine code in side-by-side windows and view the interaction between the two sets of code. Because the Quicc Engine tools are available today only in an alpha version, Freescale is initially restricting their use to third-party developers that registered for the Open Quicc Engine program. These developers include Arabella, DoGav, IndusRad, and WiPro. OEMs seeking a customized data-plane function can work with one of these developers. Once the tools are more stable, Freescale plans to begin working with a few early adopters before making the tools broadly available. The company did not set a timetable for this staged rollout. PowerQuicc has been the most popular communications processor for several years, but recently it has seen competitors such as Intel's IXP400 family offer customers access to the packet engines as well as the main CPU. This competition forced Freescale to reexamine its business model, and the development of the new Quicc Engine architecture provides a breakpoint for offering new programming support. Assuming Freescale can enable broad customer access in a timely fashion, opening its architecture should reinvigorate the PowerQuicc customer base and enable the new processors to support a wider range of applications. —Linley Complete coverage of PowerQuicc and Quicc Engine appears in our reports A Guide to Communications Processors and A Guide to Access Processors. The market for 10Gbps transceivers continues to be small, and many vendors believe lower optical-module prices could be a catalyst for market growth. One method of lowering cost is to use EDC (electronic dispersion compensation), an emerging technology that allows the use of inexpensive multimode fiber (MMF) instead of LX4, even for distances of up to 300 meters. The lower system cost enabled by EDC should increase the volume of 10Gbps ports. Although the biggest market for 10Gbps ports is enterprise, most enterprises have deployed MMF instead of LX4 fiber due to its lower cost. At 10Gbps, however, most MMF solutions are limited to a distance of only 30 meters due to impairments created by the multiple modes of light traveling through the fiber. LX4 solves this problem by using four lasers and four diodes, increasing the cost of the optical module. The 802.3aq task force is developing a new standard, called 10GBase-LRM, to enable single-laser optics for distances of up to 300 meters over FDDI-grade multi¬mode fiber. Scheduled for approval in 3Q06, this standard will use EDC to compensate for impairments incurred during fiber propagation. Chips that implement EDC compensate for modal dispersion, allowing OEMs to reduce cost by using a single laser at 10Gbps. EDC chips can be placed inside a X2/XPAK module or on a line card working with an XFP module or future SFP+ modules. The level of integration depends on the application. For a line card or X2/XPAK modules, the best approach is to integrate the EDC function with the PHY or serdes device. For inclusion inside an XFP module, integrating a CDR (clock data recovery) with EDC is a better alternative. Several vendors have taken the challenge of developing EDC chips. Scintera was first to sample a standalone EDC device. In 1Q06, Phyworks announced availability of an EDC chip that integrates a CDR. In 2Q06, Aeluros launched the AEL1003, which integrates the EDC function into the company's successful 10Gbps PHY. By the end of 2006, several other vendors including Clariphy and Quake should also sample EDC devices. With so many EDC devices available, OEMs will be able to reduce pricing on 10Gbps ports. —Jag Complete
coverage of EDC and 10Gbps PHYs appears in our new report A
Guide to High-Speed Interconnects. Xelerated and Dune Networks have partnered to deliver a complete production-ready 20Gbps Metro Ethernet switch, based on Xelerated's X11 NPU and Dune's FAP20V traffic manager. The package includes hardware and mechanical schematics, complete data-plane software, and a manufacturing partner, Sanmina-SCI. OEMs can add their own control-plane software or acquire a complete control plane from a third party, in either case getting to market in as little as three months. This offering simplifies the OEM's design task while enabling differentiation in the control plane. Although Broadcom and Greenfield enable similar systems, their fixed-function solutions hard-code the data plane. —Linley Complete coverage of Xelerated and Dune appears in our report A Guide to Network Processors.
The new edition of A Guide to High-Speed Interconnects provides updated coverage of interconnects for 10Gbps PHYs for optical interconnects, 10Gbps PHYs for copper interconnects, backplane transceivers, and chip-to-chip interconnects that include PCI Express, RapidIO and HyperTransport. We deliver the detailed information you need to evaluate the performance, feature sets, and architecture of each covered product and highlight strengths and weaknesses in a consistent, easy-to-compare fashion. We examine competing specifications and the vendor activity behind each technology, provide an objective assessment of the products, as well as project market trends and likely winners. Here are some of the many highlights you will find in this new edition:
The
report provides up-to-the-minute coverage of the developments
in this hot market. A
Guide to High-Speed Interconnects is
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