Editor: Linley
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Missed our seminar on Embedded Network Security Design? You can download the proceedings for FREE and get the latest information from Freescale, AMCC, SafeNet, Cavium, Hifn, Sensory, Tarari, and The Linley Group. For a complete program listing and download instructions, visit our web site. Yesterday at IDF, Intel announced its first embedded processor based on its Core 2 Duo processor. Code-named Merom, this 65nm processor includes two CPUs operating at 2.16GHz. More important, these CPUs implement Intel's new 64-bit architecture and deliver about 10% better per-clock and per-watt performance than the Pentium-M CPU used in earlier "Dothan" and "Yonah" products. At 34W TDP and $423, the 2.16GHz Merom targets high-end control plane, storage, and security applications. Intel also announced a less expensive version ("Conroe"), which costs $217 but burns 65W, mainly for kiosks and other PC-like applications. Merom offers better single-thread performance than any other embedded product under 40W, and it includes a fast FPU, SIMD (SSE3) processing, 64-bit compatibility, and a generous 4MB cache. Although the new processor fills out the high end of Intel's embedded line, we expect Merom derivatives to eventually filter down to lower price and performance points. For example, a 1.66GHz version with 2MB of cache should dissipate less than 20W while offering better performance than the equivalent Yonah while adding SSE3 and 64-bit support. Prices for Merom should fall to about $200 by next summer, although the chip's relatively large die size may prevent further drops. Now that Intel has put more emphasis on performance per watt rather than just performance, its processors are becoming more competitive. Dothan and Yonah compare well against high-end PowerPC and AMD processors, and Merom does a bit better. Intel still lags in integration, but customers willing to add system logic will get a performance boost from Merom. —Linley The market for PCI Express (PCIe) switch chips continues to heat up with two product announcements yesterday at IDF. PLX Technology introduced the first 48-port switch chip, and Pericom expanded its product line with the introduction of multiple switches as a part of its Packet24 family. These products can be used in servers, blade servers, embedded systems, and networking applications. In servers, these switches can fan-out the PCIe bus to provide more adapter slots, and in blade servers they can be used on the backplane. For networking and embedded applications, PCIe switches connect various peripherals to the host processor. PLX was one of the first companies to introduce PCIe switch and bridge chips. The company currently offers the broadest family of PCIe switches, ranging from 8 lanes to the new 48-lane switch, the PEX 8548. The PEX 8548 will be useful for high-performance applications such as peer-to-peer switching and dual-ported graphics for multi-monitor systems. This device also connects multiple coprocessors and I/O devices to an embedded or network processor. Compared with PLX's earlier devices, the PEX 8548 improves latency and the maximum payload size, improving performance. Pericom is adding a family of PCIe switches to its earlier 4-lane switch. The Packet24 family includes 24-lane, 16-lane, and 12-lane devices, each of which can be configured to support different number of ports. Compared with the PEX 8548, the Packet24 chips support a similar set of features, including peer-to-peer switching and cut-through or store-and-forward modes. Pericom plans to differentiate its products with features such as weighted-round-robin arbitration and power-management modes. Driven by the economies of scale of the PC platform, PCI Express is being adopted in non-PC platforms as well as in embedded processors. This broad deployment creates opportunities for PCIe switch vendors and should create a growing market for the next few years. With the broadest product line and major design wins, PLX is the early leader and continues to expand its product line. Pericom is following up on its commitment to broaden its product line for PCIe switches. In the next six months, we expect IDT and NEC to deploy new switch products that offer OEMs more choices for using PCIe switching and thereby increasing the interconnect's deployment across a diverse range of applications. —Jag Additional
coverage of PLX and Pericom appears in our report A
Guide to High-Speed Interconnects. Today at IDF, Intel announced its first 90nm XScale products, single- and dual-CPU processors that operate as fast as 1.2GHz. The IOP340 family also provides XOR and RAID6 acceleration, PCI-X and PCI Express, and 512KB of L2 cache per CPU, making them ideal for storage HBAs and high-end RAID controllers. Despite selling most of its XScale products and design team to Marvell this summer, Intel says it will continue to produce IOP products for the storage market. The fact that Intel codeveloped the new chips with Emulex, however, shows that Intel's interest in this market may be driven more by partners in the future. —Linley Complete coverage of Intel's new IOP340 family appears in our new report A Guide to High-Speed Embedded Processors. Earlier this week, Rambus demonstrated and announced availability of its IP for PCI Express Gen2, which increases the data rate from 2.5Gbps to 5Gbps. Expected to be finalized at the end of the year, the Gen2 standard should be attractive for graphics coprocessors and 10G Ethernet controllers. The IP from Rambus includes the PHY and the digital controller. Rambus was one of the first vendors to offer IP cores for PCIe PHYs and consequently captured the most design wins. Its IP enabled vendors like PLX Technology to introduce the first PCIe switch products. As a proven PCIe supplier and the first vendor to offer Gen2 IP, Rambus offers a safe path and is in a good position to win the first wave of Gen2 designs. —Jag Additional coverage of Rambus and PCIe Gen2 appears in our report A Guide to High-Speed Interconnects. Last week, Solarflare offered the industry's first demonstration of 10GBase-T or 10Gbps Ethernet over copper cabling. The startup demonstrated operation over up to 100m of Cat6a cable and up to 55m of Cat6 cable. This proof-of concept demonstration sets the stage for 10GBase-T products to appear next year. Solarflare plans to sample a three-chip set, and we expect Teranetics to sample competing devices by the end of 2007. Although Solarflare should be able to generate revenue from reference platforms, the success of its first commercial product will hinge on its power dissipation. This initial product will be challenged to meet the industry's requirement for 5W or less for a 10GBase-T PHY. Further optimizations, from Solarflare or competitors, are likely to be required before OEMs commit greater volume to 10GBase-T PHYs. —Jag Additional
coverage of Solarflare and 10GBase-T appears in our report
A Guide to High-Speed Interconnects.
Join us on November 1 for a Linley Tech seminar on processors and FPGAs for network systems. The seminar is designed to help system designers who are seeking a high-speed embedded processor or a high-end FPGA for use in networking or communications equipment. The program features technical presentations from leading suppliers of these devices as well as new and innovative entrants. Linley Gwennap, principal analyst at The Linley Group, will begin the day with an overview of the embedded processor market and technology trends, including multicore and multithreaded designs and integrated coprocessors. AMCC, Cavium, Freescale, IBM, and others will present their newest processors, including a product that has not yet been announced, and explain how they can be used in typical networking applications. The afternoon session will begin with Joe Byrne, senior analyst at The Linley Group, discussing how FPGA vendors are customizing their products and creating advanced architectures specifically for network systems. We will then hear Cswitch and other vendors describe the products and technologies. The day will close with a panel discussion covering trends in network system design. The seminar is targeted at system designers, OEMs, network-equipment vendors, software developers, service providers, carriers, press, and the financial community. The seminar is not targeted at chip companies. Regular admission is $495, but is free to qualified individuals who register by October 27. The Linley Group reserves the right to determine attendee qualification. This Linley Tech seminar will be held at the Marriott Hotel in Santa Clara. Space is limited; register today to reserve your place. This seminar is sponsored by Freescale, AMCC, Cavium, Cswitch, and
The Linley Group. Now in its 3rd edition, A Guide to High-Speed Embedded Processors has been extensively revised to cover new products and trends in the embedded market. In particular, we examine the shift from standalone to integrated processors and the shift from single-CPU to multicore. We also provide market size and market share by vendor, instruction set, and application. This edition covers many recent products and events:
Unlike typical market research, this report provides technology analysis and head-to-head product comparisons. Which processors will perform best on your application? What features do they offer to simplify your design task? How is likely is the company to deliver on its roadmap? Only The Linley Group's unique technology analysis can provide this forward-looking view. We separate the fact from fiction and provide the technology analysis you need to make informed business decisions. For more information on this new edition, visit our web site. To receive The Linley Wire via e-mail, click here
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