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Missed our seminar on high-speed processors and advanced FPGAs? You can download the proceedings for FREE and get the latest information from Freescale, AMCC, Cavium, Cswitch, IBM, The Linley Group, and others. For a complete program listing and download instructions, visit our web site. Diplomat-IP NPU Targets DSLAMs Last month, TranSwitch announced a new member of its Diplomat access processor line, the Diplomat-IP. Targeting DSLAM line cards, Diplomat-IP is based on a hardwired packet-processing engine designed to support the features outlined in the DSL Forum's TR-101 document. Its packet interfaces include a pair of Utopia2/POS-PHY and a pair of GbE interfaces. Reducing system cost, the chip dissipates a meager 3W and integrates a MIPS CPU to handle control-plane functions such as IGMP subscription requests. The chip's two 16-bit DDR2 memory interfaces further reduce system cost but may make it difficult for Diplomat-IP to achieve its rated 3.2Gbps throughput. If achievable, this rate bests that of most competing access processors, including the Agere APP300 and Wintegra WinPath2. The main drawback to Diplomat-IP is lack of flexibility. Most competing devices, including TranSwitch's slower Diplomat-A and Diplomat-E, are programmable and therefore can be adapted to custom or evolving requirements not included in TR-101; Diplomat-IP cannot. With its new device, TranSwitch renews its commitment to access processors. Narrowly targeting the large DSLAM line-card opportunity provides focus but puts the company in the thick of competition. Not only must the company compete with Agere, Wintegra, and other independent access processor suppliers, it must compete with DSL transceiver suppliers, which also supply complementary (if not complimentary, given the DSL pricing environment) access processors. Diplomat-IP's performance and system cost give it key advantages in the competition for high-density, low-cost ADSL2+ and VDSL2 line-card designs. —Joe Complete coverage of the Diplomat-IP appears in our new report A Guide to Access Processors.
Last month, EZchip and Marvell announced that they are developing a network processor that combines technologies from both companies. The companies provided few details about this device, which targets carrier Ethernet equipment. We expect it is based on the existing NP-2 design but will add Marvell switch interfaces. We expect the new NPU to reach production in 2008. Although Marvell relabels and sells products such as Dune's switch fabric, the agreement apparently does not give Marvell the option to sell existing EZchip NPUs. The new chip does not affect EZchip's previously disclosed roadmap, which includes the NP-3 and NP-4. Thus, the new NPU may be intended to serve selected customers while the NP-2 and its successors serve the broader market. Working with Marvell should help EZchip penetrate customers that it could not win on its own. The NP-2 has been quite successful so far, with EZchip reporting more than 70 design wins for the chip. Many of these wins are on line cards, which ship in far greater volume than the services cards where the NP-1c found a home. The market for 10Gbps NPUs is growing rapidly, and EZchip is well positioned to grow with this market. The partnership with Marvell underscores the desirability of EZchip's technology. —Linley Complete coverage of EZchip's products appears in our report A Guide to Network Processors. Recently, Xilinx announced its Virtex-5 LXT FPGA platform, which adds to the Virtex-5 3.2Gbps serdes, hard-wired PCI Express, and GbE MACs. The LXT family consists of six devices that range from 30,000 to 330,000 logic cells. Xilinx is sampling four of the lower density devices now and plans to sample the larger devices by mid-2007. OEMs looking for embedded CPUs or serdes at greater than 3.2Gbps will need to stay with Virtex-4 or wait for the Virtex-5 FXT devices, which should sample in 2007. Download Xilinx's presentation on the new Virtex-5 LXT as part of our recent seminar proceedings. Dune, one of few surviving fabric/traffic-manager vendors, introduced a new interface to connect its traffic manager or fabric to NPUs, ASICs and FPGA devices. Named SPAUI, this new interconnect combines the channelization and flow control of SPI-4.2 with the serial high-speed characteristics of XAUI. For greater compatibility, SPAUI can also default to a straight XAUI interface. SPAUI competes against the Interlaken specification, which is promoted by Cortina and Cisco. Although Interlaken is more comprehensive than SPAUI, it lacks backward compatibility with XAUI. The success of these interfaces may depend upon the ASICs and FPGAs that OEMs currently have in development. --JB Complete coverage of Dune's products appears in our recent report A Guide to Backplane Switch Chips.
Now in its
3rd edition, A Guide
to Access Processors has
been extensively revised to bring you the very latest developments
in the Access NPU market.
This report is now available for immediate delivery. For more information on this new edition, visit our web site.
Portable
Design: Mobile
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