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A Guide to Broadband Interface Chips is now available for immediate delivery. Are you up to speed on the emerging trends in the fast-moving VDSL2 and PON markets? For more information, visit our web site. web site. Today, Broadcom announced new transceivers for X2 optical modules and line cards. The BCM8706 is designed to meet the IEEE 802.3aq, or 10GBase-LRM, standard, which defines 10Gbps transmission over legacy MMF fiber. The BCM8706 includes transmit pre-emphasis, which allows it to be used with SFP+ modules in line cards. Transmit pre-emphasis compensates for impairments due to the long trace lines from the chip on the line card to the SFP+ module. Unlike early LRM products that use analog techniques, the BCM8706 uses digital signal processing. As it did for the first Gigabit Ethernet PHYs, Broadcom is attempting to use DSP technology as a differentiator for 10Gbps PHYs. The company claims to enable loop lengths of up to 300 meters, exceeding the 220-meter reach specified in the standard. Whereas most competing devices use 130nm process technology, the BCM8706 is fabricated on 90nm technology. This process improvement should reduce power dissipation, although Broadcom did not disclose the power of its new device. The BCM8706 is currently sampling, and Broadcom expects to qualify it for production in 2Q07. Broadcom's digital design should scale well with future process improvements, ultimately enabling dual-port and quad-port PHYs as well as well as 10Gbps switch chips with integrated PHYs. Broadcom is targeting X2 support to win modules for Cisco designs, however, the company is later than Scintera, Vitesse (formerly Big Bear), AMCC, and Aeluros. Consequently, the company best opportunities are likely to be for line cards with SFP+ modules. We expect this design activity to start in 2007. Although Broadcom is chasing the early LRM-PHY entrants, the company has a broad product portfolio that it can use to create an advantage over its startup competitors. —Jag Additional coverage of 10Gbps PHYs appears in our report A Guide to High-Speed Interconnects. We recently completed a white paper on the subject of 10G Ethernet adoption in volume servers. Here, we highlight some of our thoughts on the chip-level requirements for high-volume adoption. The complete white paper is available in PDF format on our web site. For GbE, LAN-on-motherboard (LOM) designs drove adoption in servers into the millions of ports. Single-chip controllers that integrate a MAC with a GbE-over-copper PHY enabled these LOM designs. But the advent of blade servers has created a new type of embedded Ethernet design that differs from traditional LOM designs. Blade-server backplanes use serdes links like those used to connect fiber modules. Because the GbE controller on the server blade connects to the backplane rather than an RJ-45, it does not require a 1000BASE-T (or "copper") PHY. For 10GbE, the difference between standard-server LOM and blade-server implementations is crucial; blade-server implementations are not dependent on the availability or maturity of 10GBase-T PHY components. By contrast, server LOM implementations will be constrained by the high cost, power dissipation, and footprint of early 10GBase-T PHY designs. At the end of 2006, the state of the art in 10GbE controller chips is a single-chip design that connects to PCIe on the host side and has a XAUI port for connecting to a backplane or optical module. The lowest-power designs dissipate 8–10W, and some designs require no external memory. These chips represent a single-chip 10GbE design for server blades, but standard LOM designs require the addition of a PHY or optical module. The first 10GBase-T PHY implementations will require two or three chips and will dissipate about 10W. We do not expect lower power single-chip products to sample until 2008. Thus, in 2007, a 10GbE LOM design will require three or more chips and dissipate about 20W. Clearly, 10GbE technology will have to mature significantly before it can be broadly adopted in LOM designs. On the other hand, the current state of technology is acceptable for 2007 blade-server designs. As a result, the fast growing blade-server segment should be a key driver of high-volume 10GbE adoption. —Bob Today, the OIF announced the final release of its implementation agreement (IA) of the scalable system packet interface (SPI-S). SPI-S is a channelized, streaming-packet interface that works with previously developed OIF standards. SPI-S builds upon the widely deployed SPI-4.2 interface and operates over the OIF-defined CEI (common electrical interface), which operates at up to 11Gbps for short-reach and long-reach applications. Multiple serial lanes can be combined to scale the bandwidth. In the future, SPI-S may be used with the CEI-25, which extends the serial data rate to 25Gbps. SPI-S maintains the channelization and flow control specified in SPI-4.2. It uses industry-standard 64b/66b framing or optionally the protocol defined in the CEI specification (CEI-P). The CEI-P defines forward error correction (FEC), which is useful feature when data rates exceed 10Gbps. Using standard framing, however, will allow silicon designers to reuse existing development libraries. SPI-S is agreed upon by the OIF members, which include more than 100 manufacturers. SPI-S competes directly against Interlaken, which has been promoted by Cortina System and Cisco Systems. It also competes against SPAUI, which is promoted by Dune. Compared to SPI-S, Interlaken was announced earlier, and we suspect Cortina has products under development. Although there are no products announced on either of these interconnects, SPI-S becomes the front runner on the basis of its compatibility and the number of vendors approving the specification. —Jag Coverage of other high-speed standards appears in our report A Guide to High-Speed Interconnects.
Now in its eighth edition, A Guide to Metro Network Processors brings you up to date on NPUs typically deployed in metro applications. The report focuses on mid-range (OC-48) and high-end (10Gbps to 40Gbps) NPUs as well as configurable packet processors that compete with NPUs for Metro Ethernet designs. Here are some of the many changes you will find in this new edition:
Now that NPUs are finally getting traction, get the information you need from the analysts who have been covering this market since its inception. Order by December 28 to get a special prepublication discount. For more information on this new edition, visit our web site. On January 31, The Linley Group will host the first seminar of its Linley Tech 2007 series. This one-day event will focus on CPU cores and other licensable intellectual property (IP) and is intended for designers of ASICs and SoCs (systems on a chip). Leading IP vendors will explain how their technology can be used in networking and communications applications. Get the information you need to jumpstart your design! Attendance is free to qualified attendees; others pay $495. The seminar will open with a presentation from The Linley Group highlighting recent trends in intellectual property for networking. The program includes a session on CPU cores for ASICs and SOCs, featuring presentations on how to get the most out of popular ARM, MIPS, Power, and Tensilica CPUs. The event also includes a session on other IP for networking, including security, high-speed interfaces, and wireless technology. Full details of the program will be announced in January. This Linley Tech seminar will be held in San Jose at the DoubleTree Hotel. Mark your calendars and register now at our web site. Your free attendance is made possible by our event sponsors: Tensilica, SafeNet, MIPS, Rambus, and ARM. To receive The Linley Wire via e-mail, click here
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