The
Linley Wire
Independent
Analysis of the Networking-Silicon Industry
Volume 7, Issue 1
January 11,
2007
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Editor: Linley
Gwennap
Contributors: Bob Wheeler, Jag
Bolaria, Joseph Byrne
In
This Issue
A
Guide to Metro Network Processors is now available for
immediate delivery. Get
the latest information on mid-range (OC-48) and high-end (10 - 40Gbps)
NPUs typically used in metro applications. The report also covers
configurable packet processors that compete with NPUs for Metro-Ethernet
designs.For more information, visit our
web site. web
site.
Conexant Upgrades
VDSL2 Products
Last week, Conexant announced availability of its latest products
for VDSL2. These include the Accelity 2 chipset for the central
office (CO) and a highly integrated chip for CPE. The CPE device
is the more interesting and differentiated of the two products.
The CPE chip integrates a VoIP engine for two voice channels
and a network processor (NPU) for features such as QoS. In
most cases,
the embedded NPU should eliminate the need for an external
services processor.
Conexant offers one version for VDSL2 profiles up to 30a (100Mbps
upstream and downstream) and another version for VDSL2 profiles
up to 17a. Although Conexant is not the first vendor to announce
an integrated DSL gateway processor, it is the first to offer
such a product for all VDSL2 profiles. The CPE device offers
interfaces
to support most home networking technologies, including 802.11a/b/g/n,
MOCA (Multimedia Over Coax Alliance), HomePNA, Gigabit Ethernet
and HomePlug A/V. The company has also taken the lead by
offering versions that support channel bonding. Bonding
allows telcos
to offer high bandwidth over longer loops, allowing them
to service more customers.
For
the CO, Accelity 2 offers few improvements over the company's
earlier devices. The new product consists of an 8-port
data pump, a 4-port AFE, and third-party line drivers.
We believe
this device
supports profiles up to 17a, which should be acceptable
for most CO applications. Although the CPE devices integrate
QoS support,
the CO chip set requires an external chip for these features.
Although the CO chip set offers few differentiators, Conexant
has used its
market position to win designs at several OEMs. The combinations
of a proven CO product and a leading CPE product should
put
Conexant among the leading VDSL2 suppliers. —Jag
Additional
coverage of Conexant's VDSL2 products appears in our new report
A Guide to Broadband Interface Chips.
nCipher Acquires Britestream's Assets
UK-based security specialist nCipher has acquired the assets
of Britestream Networks for an undisclosed but modest amount.
nCipher
had been a Britestream customer since 2005, and the deal allows
the company to continue shipping board-level SSL accelerators
based on Britestream chips.
Austin-based Britestream followed a meandering path. The startup
was founded in March 2000 under the name Layer N Networks to develop
a unique type of security processor for high-speed SSL applications.
After several delays, the company sampled its UltraLock SSL processor
in 4Q03. During 2004, the company reorganized itself as Britestream,
introduced board-level (SSL NIC) products, and began selling subsystems
to VARs and system integrators. Britestream's most recent product
was a single-port GbE NIC rated at 350Mbps of encrypted-traffic
throughput and 10,000 SSL transactions per second.
Until recently, UltraLock remained the only SSL product with a
single-chip flow-through design. Because SSL is a Layer 5 protocol,
a flow-through SSL chip must terminate the TCP connection before
applying the SSL protocol. Compared with conventional SSL accelerator
cards, Britestream's design was more secure and reduced host-CPU
utilization. But these advantages came at a steep price when compared
with conventional SSL accelerators from Broadcom and Cavium.
The
nCipher deal marks the end of the road for a startup that targeted
too narrow a niche. Lookaside SSL accelerators adequately serve
the bulk of the market, limiting Ultralock's appeal to a small
piece of what has remained a small overall market. In this case,
unique and superior technology couldn't overcome entrenched competition
that was good enough. —Bob
Complete
coverage of SSL accelerators appears in our report A
Guide to Security and Content Processors.
Brocade
Acquires Silverback
This
week, Brocade announced that it has acquired storage-processor
startup Silverback Systems for an undisclosed amount, which
we expect is significantly less than $10 million. This
is Brocade's
third acquisition in the last 10 months—the other two
were NuView and McData. With its focus on data centers, Brocade
acquired
Silverback for its end-point technology, which includes TCP
termination and iSCSI processing.
Founded in 2000, Silverback was in production with its iSNAP21xx
storage processors and had several customers, including Network
Appliance. In 2Q06, Silverback raised $16 million to develop
its next-generation products. The company was developing
a 10Gbps storage
processor but had not publicly announced the product. At
the time of its acquisition, Silverback had 38 employees
- most
of them
will be joining Brocade.
Although Brocade is not a silicon supplier, it plans to continue
supporting the existing Silverback customers. We do not
expect the company to offer a standard version of the 10Gbps
processor
that Silverback was developing. Instead, we expect Brocade
to use this technology to develop a 10Gbps ASIC for internal
consumption.
Although
Silverback had funding to complete its follow-on products, the
startup would have needed additional funding
before it
could see a significant return from the slow-developing
iSCSI market.
Consequently, the company's investors lost confidence,
and Silverback had no alternatives outside of an exit.
This acquisition
should
help Brocade develop 10Gbps ASICs for iSCSI and Fibre
Channel gateways. —Jag
Linley Tech Announces Program for January 31 Seminar
The first seminar in the Linley Tech 2007 series will cover
CPU Cores and other licensable intellectual property (IP)
and is intended
for designers of ASICs and SoCs (systems on a chip). This event
will be held on Wednesday, January 31, at the DoubleTree Hotel
in San Jose. The complete program for this seminar is now available
on our web site. The presentations will include:
- Linley
Gwennap, principal analyst at The Linley
Group, will provide
an overview of CPU and IP.
- Mike
Uhler,
CTO at MIPS Technologies, will present "Improving
Performance Using Multithreading."
- Steve
Singer, a systems engineering manager at SafeNet, will present "Networking Security in Silicon"
- Sumit
Gupta, a product marketing manager at Tensilica, will present "Networking
Applications for Xtensa Configurable CPU Cores."
- Toby
Foster, a system architect
at Freescale,
will present "Custom
ASICs Featuring PowerQUICC and StarCore Technologies."
- Satish
Premanathan, Chief Architect at Wipro Technologies, speaking
on "Integrating RF Technology in a Wi-Fi SoC."
- Dave
Steer,
Director of Enterprise Solutions at ARM,
will present "Implementing
High-Speed Consumer Networking Using ARM."
- Harry
Linzer, a senior engineer at IBM, will present "Power
CPU Cores Without All the Power."
- Prakash
Rashinkar, a director of engineering at Rambus, will
present "Integration:
The Hidden Cost of IP."
Don't
miss the opportunity to hear these distinguished technical speakers
discussing the latest products and design trends.
This Linley Tech seminar will be held in San Jose at the
DoubleTree Hotel. Mark your calendars and register now
at our web site. Your
free attendance is made possible by our event sponsors:
Tensilica, SafeNet, MIPS, Rambus, IBM, and ARM.
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