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Time is running out -- register this week to reserve your place! On Jan 31, we'll present a Linley Tech seminar on CPU cores and other licensable intellectual property (IP). Leading IP vendors will explain how their technology can be used in networking and communications applications. The seminar is intended for designers of ASICs and SoCs. Qualified attendees earn FREE admission, courtesy of our sponsors Freescale, Tensilica, SafeNet, MIPS, Rambus, IBM, and ARM. For a complete program listing and registration information, visit our web site. 10GBase-T
Is Coming, Ready Or Not Tehuti's announcement included three new products: single- and dual-port 10GBase-T NICs (TN7588-S/TN7588-D) as well as a dual-port CX4 NIC (TN7585-D). Like Chelsio, Tehuti is using Teranetics' TN1010 10GBase-T PHY. All three NICs are based on Tehuti's latest PCIe controller design, the TN3016, which is implemented using an FPGA. Although the dual-CX4 NIC is currently sampling, Tehuti did not announce pricing or availability for its 10GBase-T NICs. For its part, Teranetics has not formally announced the TN1010, which is described as a single-chip 10GBase-T transceiver. Teranetics' only competition comes from Solarflare, which is sampling the multi-chip 10Xpress SFX7101 10GBase-T transceiver. Both vendors claim 10GBase-T compliance for their respective products, but interoperability between the competing products has not yet been demonstrated. Neither vendor has disclosed details such as power dissipation, which we expect to fall in the 8-12W range for these first-generation transceivers. Meanwhile, no OEM has announced a switch with 10GBase-T support, so no infrastructure exists to support the new Chelsio and Tehuti NICs. Until switch support becomes available, the NICs are merely interesting test vehicles and will help prove out the new 10GBase-T PHY technology. Still, these announcements show that the race is on to bring 10GBase-T to end users in 2007. —Bob Complete coverage of Chelsio and Tehuti appears in our report A Guide to Gigabit and 10G Ethernet Chips.
OEMs can use the CS3477's 4:1 intelligent oversubscription to develop a 10GbE line card consisting of up to 16 ports. Such a line card would have four CS3477 devices connected to a 40Gbps processor through four Interlaken interconnects. To manage oversubscription, the CS3477's traffic manager classifies packets and polices to a specified rate on the basis of VLAN, IPv6, MPLS, and TCP headers. With this announcement, Cortina has extended the MAC product line it acquired from Intel by adding the industry's highest bandwidth MAC aggregation chip. Cortina is also unique in offering a MAC aggregation device with the Interlaken interface, giving the small company an edge in gaining design wins at Cisco. Integrating XFI allows the CS3477 to connect directly to XFP modules, which are used in routers at Cisco but not in the OEM's enterprise switches. Because no announced network processors support Interlaken, other OEMs must develop ASICs or use the Virtex-5 FPGA when designing with the CS3477. With SPI-S emerging to address the shortcomings of SPI-4.2, many vendors and OEMs may select SPI-S over Interlaken, leaving the future of that effort in doubt. Although Cortina has no current plans to support SPI-S, the company may need to do so to address the broader market. —Jag Additional coverage of Cortina appears in our report A Guide to High-Speed Interconnects. This week, Broadcom announced the latest products in its StrataXGS III line of GbE/10GbE switch chips. The new BCM5651x chips update the BCM5650x products, which first sampled about two years ago. The 5651x chips maintain the same port configurations as their predecessors but offer new features, which Broadcom has branded BroadShield, aimed at improving security. Key enhancements include improved classification capabilities and support for virtual router forwarding (VRF). The 5651x devices are currently sampling. —Bob Complete coverage of Broadcom's StrataXGS products appears in our report A Guide to Gigabit and 10G Ethernet Chips. Save the date! Mark your calendars for March 13 for a Linley Tech seminar on Metro Ethernet Equipment Design. The program will cover chips for both data-plane and control-plane processing in Ethernet aggregation, Ethernet access, and Ethernet-over-Sonet/SDH equipment. This seminar is sponsored by Freescale, AMCC, Xilinx, EZchip, and The Linley Group. Details of this event and additional sponsors will be announced soon. To receive The Linley Wire via e-mail, click here
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