Editor: Linley
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Proceedings available. If you missed our seminar on CPU Cores and IP for Networking you can download the proceedings for FREE and get the latest information from Freescale, Tensilica, SafeNet, MIPS, Rambus, IBM, ARM, and The Linley Group. For a complete program listing and instructions, visit our web site. Tolapai Boosts Intel in Embedded Details emerged this week about an unannounced Intel product code-named Tolapai. A report from HKEPC (Hong Kong) indicates that the new device combines a Pentium-M CPU at up to 1.2GHz, crypto and packet engines, and a broad set of system interfaces (the north and south bridge, in PC parlance). Unlike Intel’s previous and ultimately short-lived integrated x86 chips, Tolapai has no graphics unit and is squarely positioned for the embedded market. The chip is due in late 2007. To date, Intel’s success in the embedded market has mainly been in “PC-like” applications such as kiosks, POS terminals, and industrial control. Intel’s x86 processors are also often used in NAS and high-end security equipment. But the cost, power, and footprint of an Intel CPU plus north and south bridges has kept Intel out of many higher-volume designs, which instead use integrated RISC processors. Tolapai aims to level the playing field by integrating a memory controller, PCI Express, Gigabit Ethernet ports, USB, serial ATA, and other common interfaces, much like competing MIPS, ARM, and PowerPC chips. Tolapai even includes CANbus and IEEE 1588, which are used in automotive and industrial applications, respectively. The integrated crypto and packet engines could make the new chip attractive for security appliances and networking equipment. However, Tolapai burns significantly more power than comparable integrated RISC processors. Thus, while the new device reduces the penalty for using x86, it does not entirely eliminate it. We expect Tolapai to increase Intel’s market share in embedded applications where x86 software compatibility is attractive, but not in high-volume applications where cost and power are paramount. —Linley Complete coverage of competing products appears in our report A Guide to High-Speed Embedded Processors. On Monday, Raza Microelectronics (RMI) added a midrange product family to its MIPS-based lineup. The new XLS uses the same multithreaded CPU and acceleration engines as the high-end XLR, but comes with only one or two CPUs. By scaling down the memory and I/O throughput accordingly, RMI can offer the XLS processors at prices ranging from $150 to as low as $30. At these prices, the new chips neatly fill the gap between the XLR and RMI's low-cost Alchemy MIPS processors. Like their big brothers, the XLS processors operate at speeds of up to 1.2GHz. Each 64-bit CPU supports four threads, improving efficiency for packet processing and other applications that can be divided into several separate tasks. The highly integrated processors include up to four memory controllers, up to eight GbE MACs, PCI Express, dual USB, and other system interfaces. Some models of the XLS include crypto and compression engines that operate at up to 2.5Gbps. Samples are due next quarter, with production by the end of the year. Although the XLR has been gaining design wins in high-end security and networking equipment, relatively few applications need an 8-CPU, 32-thread processor. The XLS hits mainstream price points, making it well suited to security appliances, wireless access points, and similar higher-volume designs. RMI has, surprisingly quickly, built a line of compatible processors that spans applications from cell phones to core routers. Now, the startup must figure out how to sell processors to such a broad range of customers. —Linley Complete
coverage of the XLR appears in our report A Guide
to Security and Content Processors.
Last week, Solarflare announced its first controller chip for 10G Ethernet. This is the first new controller from the company since its merger with Level 5 Networks in April 2006. Whereas Level 5 sold adapters (NICs) both to OEMs and to end-user channels, Solarflare is selling only chips to OEMs. As a result, the company announced the SFC4000 Solarstorm controller chip along with three adapter reference designs for 10GBase-T, optical (XFP), and 10GBase-CX4 media, respectively. The 10GBase-T design uses Solarflare's 10Xpress PHY chip set. The SFC4000 integrates a PCI Express x8 host interface and one XAUI port. Although the chip supports optional external SSRAM, no external memories are required for typical designs. The SFC4000 is a stateless design that implements some new and unusual offloads. For example, the chip supports Microsoft's receive-side-scaling (RSS) as well as CRC32 offload for iSCSI. Solarflare says the SFC4000 is also capable of supporting Intel's QuickData, which is the data-movement offload developed as a part of IOAT. Finally, the new chip supports hardware offloads for virtualization. By using a relatively simple stateless design, Solarflare was able to deliver standout power dissipation; the SFC4000 consumes little more than 2W. This metric becomes particularly important for 10Gbase-T designs, as the first-generation copper PHYs consume as much as 12W. Solarflare also stands out as the first vendor to offer both a 10GbE controller and 10GBase-T PHY. As compared with competing controller vendors, this gives Solarflare greater control over the solution cost for 10GBase-T NIC designs. Today, however, OEMs are primarily purchasing board-level (NIC) products for 10GBase-SR or CX4, and Solarflare does not sell its reference designs in production volumes. But as Solarflare's initial entry into 10GbE controllers, the SFC4000 is a more-than-credible effort. —Bob Complete coverage of 10GbE controllers and NICs appears in our report A Guide to Gigabit and 10G Ethernet Chips. Last week, P.A. Semi announced sampling of its initial product, the PWRficient processor. The new chip contains two PowerPC CPUs running at up to 2GHz along with high-speed interfaces including two 10G Ethernet MACs and PCI Express. Despite the high speed, the 65nm chip dissipates just 13W (typical) at 2GHz and 6W at 1GHz, significantly less than competing devices. The company has 10 initial customers for its processor, which is well suited for control plane, storage, and security applications. The fact that the design has met its original speed and power goals is an impressive accomplishment. —Linley This week, PCI-SIG announced the PCI Express external cabling specification, which defines standard cables and connector for lane widths of x1, x4, x8, and x16. Using sideband signaling, the specification maintains backward compatibility to existing silicon and software. Although the SIG plans to offer an enhanced specification of 5.0Gbps for PCIe 2.0, the initial cable specification supports the same 2.5Gbps as in PCIe 1.1. Target applications include external graphics, tethered mobile docking, communication equipment, and embedded application. —Jag
On March 13th, The Linley Group will host the next seminar in its Linley Tech 2007 series. This one-day event will focus on the design of Ethernet aggregation, Ethernet access, and Ethernet-over-Sonet/SDH equipment. The seminar will open with a presentation from The Linley Group highlighting Metro Ethernet design trends and providing context for later presentations. The remainder of the program will include subjects ranging from packet processing to control-plane processing to Ethernet-access platform design. Relevant chips that will be discussed include CPUs, network processors (NPUs), FPGAs, and Sonet/SDH/RPR devices. Full details of the program will be announced shortly. The seminar is intended for system designers, network-equipment vendors, OEMs, service providers, carriers, press, and the financial community. Leading chip vendors will discuss Metro Ethernet applications and how their products can be used in new designs. Get the information you need to jumpstart your design! Attendance is free to qualified attendees; others pay $495. This
Linley Tech seminar will be held in San Jose at the DoubleTree
Hotel. Mark your calendars and register now at our web site.
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