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Joseph Byrne, senior analyst at The Linley Group, will speak at the upcoming Multicore Expo on March 28 in Santa Clara on the topic of "Multicore Processors for Security and Control-Plane Applications." For more information about this event, access the Multicore Expo web site. T10: Tarari's Next-Gen Architecture At the RSA Conference earlier this month, Tarari announced its T10 Technology for content processing. Compared with Tarari's shipping T9000 chip, the T10 Technology increases performance, decreases system cost, adds features, and supports new host interfaces. Tarari is rolling out T10-based products in phases: FPGA-based PCI Express (PCIe) boards are now sampling, HyperTransport (HTX) boards will follow in early 2Q07, and a T10 ASIC is due later this year. The FPGA designs offer 5Gbps of throughput, whereas the T10 ASIC is targeting up to 10Gbps of throughput and the existing T9000 PCI-X chip delivers at least 2.5Gbps. Tarari's T10 next-generation architecture supports a superset of the T9000's features, which already included a long list of engines for regular-expression processing, XML grammar processing, encryption, compression, random-number generation, and character conversion. Tarari has added new engines for XML threat management (XTM) and AES encryption. The regular-expression engines were enhanced to support Perl-compatible regular expressions (PCRE) and cross-packet inspection. Unlike the T9000, the T10 architecture processes packets on the fly rather than waiting for the complete packet to begin processing. This new "cut-through" packet flow greatly reduces latency for large packets. The T10 architecture decreases system cost by using commodity DRAM for pattern storage in place of the SRAM devices required by all previous Tarari designs. The move to DRAM also increases the T10's rule capacity by an order of magnitude. With this announcement, Tarari is introducing important enhancements to its FPGA-based designs while also showing a path to 10Gbps performance. In doing so, the company is strengthening its leadership position in XML processing and offering a competitive response to NetLogic's 10Gbps content processing chip set. If it delivers T10 ASICs as planned, Tarari should have a compelling technology advantage. —Bob Complete coverage of Tarari appears in our report A Guide to Security and Content Processors. Earlier this month, Centillium announced the Mustang 300 for ONU applications. This chip updates the company's earlier Mustang 200 device. Like the earlier chip, the new version includes two GbE MACs, an EPON MAC, and serdes, connected through an 802.1D bridge. It supports encryption and integrates a MIPS CPU. The chip enables traffic management through multiple queues, supports 256 multicast groups and up to 8 service types. Unlike the earlier device, the Mustang 300 integrates packet buffers and program memory. This integration enables an OEM to develop a simple ONU using the Mustang 300 along with an optical transceiver, PHY, and Flash memory. The company completes its ONU solution with the addition of the Zeus 2 burst-mode transceiver and software. For an IAD design, OEMs can pair Mustang with Centillium's Atlanta gateway processor. Atlanta performs the voice processing, routing, IPSec, and VPN functions typically found in a residential gateway. Integrating memory reduces system cost compared with the company's earlier devices as well compared with ONU chips from leading competitors. OFN, a Japanese OEM, has committed to using Mustang 300 for NTT deployments. Centillium has validated interoperability of the Mustang 300 against OLTs that use chips from PMC-Sierra, which ships majority of OLT components in Japan. Having missed the first wave of EPON deployments, Centillium is hoping to win more business on the basis of lower system cost. Because of the large costs to switch PON vendors, however, this strategy is more likely to bear fruit in new markets, such as Korea and China. —Jag Additional coverage of Centillium's Mustang family appears in our report A Guide to Broadband Interface Chips. In conjunction with our recent seminar on intellectual property, The Linley Group polled registrants who had used semiconductor IP about their experiences. This poll of 32 attendees found ARM to be the most popular IP vendor, despite the fact that the seminar focused on networking and communications designs and not cellular handsets. Also notable is the rapid adoption of multicore design in chips our respondents are developing. Most new designs will use more than one CPU core, with a quarter of respondents integrating four or more cores in their current design. About three quarters of respondents' current designs will operate the CPU at more than 300MHz, with a significant number at 600MHz or above. The survey also reveals that functional capability is the dominant concern and not a major source of problems. A majority of respondents reported that they choose IP foremost based on the block's functional capabilities, with the remainder indicating functionality is less important than prior use of the block, fees, and performance. While most respondents indicated they license IP mainly to save time, suggesting that they think they could develop the IP themselves given sufficient time, a substantial minority (37%) do so to gain access to technology. Not meeting functional specification was the least-cited problem respondents had with IP. However, not meeting performance targets was the most-cited problem Other oft-cited problems include poor documentation, difficulty with integration, and poor customer support. Integration difficulties are well known. They were the subject of the Wipro and Rambus presentations at the seminar, and Rambus showed other survey data indicating they are a chief issue in IP licensing. However, our results indicate that customer-service issues—documentation and support—are more important. The problems with attaining performance could also be related to customer service (e.g. promising more to customers during the sales cycle than the product can feasibly deliver or inadequately supporting customers' efforts to attaining timing closure). —Joe Complete survey results appear in the proceedings from our CPU Cores and IP for Networking seminar, available on our web site at no cost. China-based Opulan Technologies joined the access processor fray with its February 5 announcement of the IPMux DSL aggregation chip. The IPMux closely resembles the Diplomat-IP from TranSwitch (an investor in Opulan), and it appears that Transwitch is allowing Opulan to comarket its device in an attempt to gain share in China. Opulan already claims a design win at ZTE, China's second-largest telecom supplier. But with many access NPU vendors chasing a small number of DSLAM vendors, Opulan will find it difficult to gain more than regional success. —Joe Complete coverage of Diplomat-IP appears in our report A Guide to Access Processors. Join us on March 13 in San Jose for a Linley Tech seminar on Metro Ethernet Equipment Design. This one-day event will focus on the design of Ethernet aggregation, Ethernet access, and Ethernet-over-Sonet/SDH equipment. Hear the latest from leading chip vendors as they discuss Metro Ethernet applications and how their products can be used to enhance new designs. The presentations will include:
Additional talks will be announced soon. The seminar is intended for system designers, network-equipment vendors, OEMs, service providers, carriers, press, and the financial community. Attendance is free to qualified attendees. This Linley Tech seminar will be held in San Jose at the DoubleTree Hotel. Mark your calendars and register now to reserve your place. Sponsored by: Freescale, AMCC, Xilinx, EZchip, Exar, Bay Microsystems, Lightstorm Networks, and The Linley Group. The ever-increasing demand for storage, combined with changes in information management and advances in disk-drive technology, are creating new opportunities for storage silicon suppliers. A Guide to Storage Processors covers the booming market for RAID and storage-network processors, describes the emerging category of storage processors, and projects key technology and market trends. The report begins with an extensive overview of storage infrastructure--including DAS, SAN, NAS, and IP storage--then provides an overview of the key standards and technologies used in these applications. Direct-attached storage (DAS) continues to be popular, but even data stored with DAS must be protected from drive failure. Seizing the opportunity, chip companies, are supplying processors that integrate RAID acceleration, including the latest RAID6 technology. Most recent RAID processors integrate SATA/SAS interfaces to lower the cost of RAID adapters, facilitate "RAID on motherboard" designs, and enable customers to connect the newest disk drives to their servers. Storage-area networks (SAN) also continue to grow rapidly, and the affordability of iSCSI is enabling SAN technology to be used by large enterprises for applications below Tier One, as well as by small and medium-size businesses where DAS had previously been used. Specialized iSCSI target chips enable microprocessors and RAID processors in external storage systems to connect to iSCSI SANs. OEMs seeking more performance can use storage network processors that use special-purpose architectures to combine iSCSI and storage management. We bring you up to date on this market with thorough coverage of all announced products. For each vendor, the report examines the performance, feature set, and architecture of their chips, highlighting their strengths and weaknesses in a consistent, easy-to-compare fashion. Several other vendors that have not made significant public disclosures are briefly covered. The report concludes with our own comparisons of these products and our conclusions about which will fare best. Order by March 16, 2007 to get a special prepublication discount. For more information on this new report, including a preliminary table of contents, visit our web site. To receive The Linley Wire via e-mail, click here
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