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Save the date! Mark your calendars for September 13 for the Linley Tech seminar on Embedded Network Security Design. This seminar is sponsored by Freescale, AMCC, SafeNet, Intel, Tarari, and Elliptic. Details of this event will be announced soon. Cavium Enters Storage-Processor Market Cavium has announced an expansion of its Octeon multicore processor line that marks the company's entry into the storage market. Compared with previous Octeon chips, the new storage services processors (SSP) add hardware acceleration blocks for storage-specific functions. Because the new design includes updated network and I/O interfaces, Cavium also announced new network services processor (NSP) versions. With clock speeds up to 1GHz, the new Octeons will come in two package options spanning 6 to 12 cores and 2 to 6 cores, respectively. The version with up to 12 CPUs is due to sample during 3Q07, while the smaller version is due in 4Q07. The new CN55xx/57xx SSP and CN54xx/56xx NSP chips are based on the same architecture and CPU complex as the CN58xx Octeon Plus, which was announced in 4Q06 and is now sampling. For the SSP, Cavium added hardware acceleration for RAID 5/6 and iSCSI CRC32 as well as reliability, availability, and serviceability (RAS) features such as DRAM self-refresh. Both the SSP and NSP versions of the chip implement a new set of serdes-based network and I/O ports. The design includes 16 lanes that are assigned to various combinations of up to two PCI Express (PCIe) ports, eight SGMII ports, and two XAUI ports. Notably absent is direct support for SATA/SAS interfaces; customers that need these interfaces will have to add a third-party PCIe controller. Given the processing power and level of integration of Cavium's initial SSP offerings, we see them primarily competing for storage-array applications versus Freescale and PA Semi. To compete in RAID HBA and RAID-on-motherboard designs, Cavium must develop lower-end SSPs with integrated SATA/SAS ports. The initial SSP chips represent a logical entry point in the storage market and broaden Cavium's application scope. Following a successful IPO and the sampling of Octeon Plus, Cavium is demonstrating continued momentum. —Bob Complete coverage of competing RAID processors appears in our report A Guide to Storage Processors.
At FTF last month, Freescale disclosed a new roadmap for future PowerPC processors. Taking advantage of its recent alliance with IBM for IC manufacturing technology, Freescale plans to move directly from its current 90nm products to 45nm products, skipping the 65nm process node. This shift should result in a sizable improvement in performance-per-watt as well as integration. Freescale expects to sample its first 45nm devices in late 2008. The new roadmap focuses on Freescale's e500 CPU, used in the popular MPC8548 and the new dual-core MPC8572, rather than the e600 CPU used in the MPC8641. While the e600 was derived from older Apple-focused processors, the e500 was designed specifically for the embedded market, delivering nearly the same performance at much lower power levels and using less die area. Although Freescale has been slow to deploy multicore products, the new roadmap improves delivered performance by increasing the number of CPUs rather than by increasing the speed of a single CPU. Using 45nm, Freescale should be able to put at least four e500 CPUs on a single chip, doubling the performance of the 8572. To maintain efficiency, each CPU will have its own level-two cache, and the chip will also have a shared level-three cache. Derivative devices with one or two CPUs will also be available. The new roadmap accelerates Freescale's multicore plans. For customers whose software can adapt to this model, the new products should deliver more performance than in the old plan. Customers who wanted to stay with a single high-performance CPU will be disappointed, but Freescale's problems with the 8641 showed that this "fat CPU" strategy is not workable. Focusing on the e500 should improve Freescale's execution as well as the power efficiency of its processors. Unfortunately, resetting the roadmap creates a long gap until the new products become available. —Linley Additional
coverage of Freescale's PowerPC processors appears in our
report A Guide to High-Speed Embedded Processors. Infineon is acquiring the DSL business of Texas Instruments. According to The Linley Group market share data, Infineon ranked fourth in DSL revenue for 2006 and TI ranked third; combined, the two generated $347 million, more than any single vendor. Thus, this acquisition should make Infineon the leading vendor of DSL chips. TI had once been the industry leader in DSL revenue. Its highly integrated AR7 processors are popular for ADSL modems and gateways. The company's UR8 processor, however, suffered from extensive delays and did not meet its original specifications. At the same time, Broadcom introduced its own highly integrated devices and began to gain share from TI. At $205 million in 2006, TI's revenue was roughly flat in a growing market. After the UR8 fiasco, the company destaffed its DSL development team and began to seek an opportunity to sell the business. Infineon's Danube processors are also highly integrated solutions for ADSL gateways, but they have been less successful in the market, particularly outside of Europe. Unlike TI, which offers VDSL2 at only 8MHz, Infineon's VDSL2 chips support all bands up to 30MHz. Danube also offers a more powerful CPU than the UR8 has and adds encryption functions. We expect Infineon to continue to support the UR8 while attempting to shift TI's customers to Danube and its successors. Although this strategy is likely to result in some loss of customers, it will keep Infineon's R&D cost steady while providing a big boost in revenue. With Conexant and Broadcom pulling away in revenue, this acquisition makes the DSL market a three-horse race. By adopting Infineon's superior technology, TI's DSL customers could be the big winners in this deal. —Linley Complete coverage of DSL products from Infineon and TI appears in our report A Guide to Broadband Interface Chips. Reminder: last chance to register for the July 18 Linley Tech seminar on the silicon trends in enterprise and data-center networking. Qualified attendees must register by July 13 to get free admission. For details, visit our web site. Linley's Latest Column: Nikkei Electronics: Microprocessors Add Security Functions To receive The Linley Wire via e-mail, click here
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