The Linley Group

This week, Cavium brought the power of Octeon Plus to its low-cost line in the form of the CN50xx, a family of single- and dual-core MIPS processors that operate at speeds of up to 700MHz. The new processors are pin- and software-compatible with Cavium’s current CN30xx devices while offering significantly better performance. (The CN30xx tops out at 500MHz.) The new devices also burn less power, thanks to a shift from 130nm to 90nm manufacturing. Cavium expects to sample the CN50xx by December.

Despite being a relative newcomer to the processor game, Cavium has made significant advances. In the past year, the CN30xx has gained design wins in broadband gateways, 802.11n routers, and secure routers from NetGear, Cisco/Linksys, Omron, and others. The processors are also found in small/medium business (SMB) applications such as storage and security appliances and unified “office in a box” solutions. The new CN50xx fits into all of these categories, offering more performance headroom for SMB products in particular.

By making the new parts pin-compatible with the current ones, Cavium enables customers to leverage their existing board and software designs, taking advantage of the infrastructure investment that Cavium and its partners have made for the CN30xx. But this decision kept the company from adding newer interfaces such as PCI Express or serial ATA. These interfaces will probably appear in a next-generation processor next year. In the meantime, the new CN50xx should continue Cavium’s momentum in the SOHO and SMB segments. —Linley

At last month’s Intel Developer Forum, several vendors announced or demonstrated products supporting the second-generation (Gen2) version of PCI Express (PCIe). IDT demonstrated the industry’s first Gen2 switch chip, and Pericom demonstrated prototypes of its Gen2 redriver chip.

IDT’s demo coupled its PES16T4G2 switch chip with an Intel Gen2 chip set and Gen2 endpoints from ATI and Broadcom. The 16T4G2 has one upstream x4 port and three downstream x4 ports, all capable of operating at 5Gbps per lane. Like IDT’s PCIe v1.1 switch chips, the 16T4G2 supports a large 2KB maximum payload size and cut-through operation for latencies of 180ns or less. Priced at $35 in volume, the 16T4G2 is currently sampling. For Gen2 designs requiring only two downstream ports, IDT offers the 12-lane PES12T3G2.

Pericom demonstrated prototypes of its Gen2 redriver chips, which are used to extend the reach of PCIe signals. Unlike retimers, redrivers improve signal integrity without extracting clocking information. Redriver applications include driving PCIe backplanes or external cabling. Pericom’s PCIe Gen2 redrivers are due for production availability in 1Q08. The company also offers Gen2-compatible analog switch chips, which can be used for failover and other multiplexing applications. Although Pericom is shipping PCIe v1.1 packet switches, it has not yet announced any Gen2 packet switches.

For dual-socket server designs, the new IDT and Pericom chips mate with Intel’s Seaburg MCH (north bridge). Seaburg integrates 32 PCIe lanes that support 5Gbps operation for an aggregate 16GB/s of bidirectional I/O bandwidth (after 8b/10b encoding overhead). Complementary Gen2 chips like those from IDT and Pericom will help OEMs make optimal use of this massive bandwidth. —Bob

Seminar Features High-Speed Processors

The Linley Tech seminar on November 14 will feature a packed lineup of technical presentations addressing two key themes: processors for SOHO/SMB and high-speed embedded processors. The presentations will address processor architecture and design and their applications in networking and communications. Presentations will include:

Linley Gwennap, principal analyst of The Linley Group, will open the day with an overview presentation on the topic of embedded processor design and market and technology trends.
David Sonnier, a chief architect at LSI, will explain how company’s new APP2200 processor combines control-plane and data-plane engines to deliver carrier-grade performance for SMB equipment.
David Fotland, CTO of Ubicom, will describe how the company’s unique processor architecture addresses the increasing demands of the connected digital home.
Toby Foster, a system architect at Freescale, will examine the optimization of CPU design, application offloads, memory subsystems, and high-speed interfaces in dual-CPU processors.
Anant Agarwal, CTO of Tilera, will describe the company’s radical new 64-CPU architecture and how it can accelerate intrusion prevention, spam filtering, QoS provisioning, and other Layer 3-7 applications.
Mark Hayter, chief system architect at PA Semi, will describe the company’s dual-CPU Power processor, including example system block diagrams and a detailed device power breakdown.
Dan Bouvier, director of solutions architecture at AMCC, will discuss how the demands of all-IP convergence affect the design of the CPU complex, accelerators, and I/O in next-generation processors.
Raj Singh, a communications architect at IBM, will discuss how trends such as virtualization and convergence can be addressed by IBM’s system-on-a-chip technology.

Don't miss the opportunity to hear these distinguished technical speakers discussing the newest processors and design trends. This Linley Tech seminar will be held in San Jose at the DoubleTree Hotel. Mark your calendars and register now at our web site. Free admission for qualified attendees is made possible by our event sponsors: Freescale, AMCC, LSI, IBM, Ubicom, PA Semi, and Tilera.