The Linley Group

New Carrier Ethernet Chips Unveiled

At our Carrier Ethernet Equipment Design seminar held in San Jose on January 30th, four vendors disclosed new products for carrier Ethernet designs. For optical-transport equipment, AMCC disclosed its Pemaquid next-generation 10GbE FEC/mapper device. Building on the highly successful Rubicon chip, Pemaquid improves integration and reduces system cost. Whereas Rubicon has SFI-4 interfaces on both ends, Pemaquid integrates 10Gbps serial XFI on the line side and XAUI on the fabric side. Pemaquid also requires only a single oscillator versus the three PLLs required in an equivalent Rubicon-based design. Pemaquid is currently sampling to lead customers, with general sampling scheduled for March.

Danish vendor TPack announced its SoftSilicon concept, which provides FPGA-based alternatives to mapper chips and/or NPUs. TPack is essentially implementing application-specific standard products (ASSP) using Altera FPGAs as the underlying silicon. During his talk, TPack CTO Lars Pedersen described several specific products including 10G SONET/SDH framer/mapper devices and a 20G Layer 2 packet processor and traffic manager. The most impressive example, the TPWX3192, combines a 10GbE-over-SONET/SDH framer/mapper, packet processor, and traffic manager (TM) into a single Altera Stratix III device that consumes less than 22W in this design. By delivering a production-ready configurable device, TPack eliminates the customer’s need for an FPGA/ASIC design team or data-plane microcode development.

Focusing on next-generation wireless backhaul requirements, Wintegra announced its new WinIP family of products. Following Wintegra’s model for application-specific products, WinIP bundles a cost-optimized WinPath2 network processor (NPU) with a carrier-Ethernet software package. By using Wintegra’s data-path binaries, customers configure WinIP through APIs and need not write any data-plane code. WinIP is designed to meet the transport/backhaul requirements for LTE and other 4G wireless networks.

For high-end metro Ethernet designs, Xelerated announced a new version of its X11 40Gbps NPU as well as general availability of its Metro Ethernet Application (MEA) software. The new X11-d240t operates at the same 240MHz clock speed as the existing d240, but the “t”-suffix device adds new instructions to improve packet-processing efficiency. Xelerated claims the new chip delivers 20% more processing power in typical customer designs. The MEA software provides 90-95% of the data-plane code for typical line-card designs; the TM/fabric interface must still be customized to match the customer’s design. —Bob

The presentations from these four vendors, additional vendor presentations, and an introductory presentation from The Linley Group are all available for download from our website.

Last month, NetLogic announced the NL9000 knowledge-based processor, which can perform searches on anchored strings such as IPv6 address. The NL9000 is capable of 1.2 billion searches per second on keys of up to 320 bits. The device combines the company’s TCAM-based search-engine technology with the Sahasra algorithm technology that NetLogic acquired from Cypress. NetLogic is the first company to offer a hybrid TCAM/algorithm-based search engine.

The NL9000 uses three types of search technologies: TCAM, the Sahasra algorithm, and a range-encoding algorithm. TCAM technology is well suited for rules lookups, the Sahasra technology is suited for forwarding lookups, and range encoding is suited for range lookups. Using the three together delivers high search performance while reducing power dissipation. To further optimize power dissipation, the NL9000 is manufactured on 55nm CMOS and includes several power management modes. NetLogic claims the overall power can be roughly five times lower than standard TCAM-based search engines.

The NL9000 provides 64 processor engines, each of which can be mapped to a specific search technology on the basis of the searches to be performed. Using this mapping, an intelligent load balancer in the device sends packets to an appropriate processor engine. The NL9000 provides an 80-bit interface at 400MHz DDR2, producing a bandwidth of 64Gbps--enough to support OC-768 or 40Gbps Ethernet. The company claims to have several design wins at Tier One OEMs. The NL9000 is a unique device that should help NetLogic remain a leading supplier of search solutions. —Jag

This week, Vitesse introduced the VSC8664, the industry’s first quad-port synchronous Gigabit Ethernet PHY. Facing increasing bandwidth requirements, telecom carriers see Ethernet as a cost-effective means to offer greater bandwidth than T1/E1 links. Traditional telecom services like voice, fax, and modem rely on a synchronous network. Thus, in telecom applications, Ethernet must support synchronous operation. Other applications for these synchronous Ethernet PHYs include ADM-to-base station connections and cellular backhaul.

The VSC8664 PHY synchronizes operation to the incoming clock and outputs two recovered clocks. The second recovered clock is used for failovers in carrier-class systems. To reduce system cost, the VSC8664 integrates an I2C mux, which can manage multiple SFP and power-over-Ethernet (PoE) modules. Vitesse is currently sampling this PHY at the extended temperature range. With synchronous Ethernet technology, Vitesse is better positioned for carrier-class Ethernet than traditional Ethernet component vendors. —Jag

On March 19, The Linley Group will hold the next seminar in its Linley Tech 2008 series. This one-day event will cover CPU cores and other licensable intellectual property (IP), focusing on how they can be used in networking and communications applications. Get the information you need to jumpstart your chip design!

The seminar will open with a presentation from The Linley Group highlighting recent trends in intellectual property and CPU core design, providing a context for later presentations. The program features a session on CPU cores, featuring presentations on how to get the most out of popular Power, MIPS, and Tensilica CPUs in packet processing and communications applications. The remainder of the day will include subjects such as integrating security functions, high-speed interfaces, and other networking functions. Full details of the program will be announced soon.

The seminar is intended for designers of networking or communications ASICs or SoC (system-on-a-chip) products that use licensed intellectual property, including designers at equipment companies or semiconductor vendors. These designers will learn about the newest IP products as well as how to evaluate, integrate, configure, and program these IP cores for applications similar to the ones they are designing. Attendance is free to qualified attendees; others pay $495.

This Linley Tech seminar will be held in San Jose at the DoubleTree Hotel. Register now to guarantee your place. The seminar is targeted at ASIC and SoC designers, OEMs, press, and the financial community. Sponsored by Freescale, IBM, Tensilica, and SafeNet.